Research Page of Wang Yi
Interests:
My main interest lies in modeling and analysis as well as implementation
of real-time and embedded systems, in particular:
- Embedded Systems Design
- Real-Time Scheduling
- Multicore Programming
- Model-Checking of Real-Time Systems
Projects:
I am a member of the
Embedded Systems Group
at Uppsala.
Our research focus is on theories, techniques and tools
for modelling, design and validation of embedded and real-time
systems. I am also a PI of
UPMARC - Uppsala Programming for Multicore Architectures Research Center
(10-year Linne-center grant from the Swedish Research Council).
I have been involved in a number of national and european projects
in embedded systems areas, including:
-
Scalable Timing Analysis of Complex Embedded Systems
(PI, VR grant, Swedish Research Council, 2016-2020).
-
CoDeR-MP - Real-Time Applications on Multicore Platforms
(PI, with ABB and SAAB, supported by SSF 2009-2014).
-
CERTAINTY - Certification of Real Time Applications designed for mixed criticality
(site leader, FP7).
-
SAVE++ - Component Based Design of Safety Critical Vehicular Systems
(PI, with VOLVO et al, 5-year SSF program).
-
CREDO - Modeling and analysis of evolutionary structures for distributed services
(site leader, STREP project, IST-33826).
-
ARTIST - Network of Excellence on Embedded Systems Design
(core member of Modelling & Validation cluster, FP7).
-
AIT-WOODDES
- Workshop for Object OrIenTed Design and Development of embedded Systems
(site leader, FP5)
Tools:
We have developed:
-
UPPAAL for model checking
real-time systems based on timed automata (with Aalborg University).
-
TIMES for schedulability analysis
and code generation for embedded systems.
-
CATS for
compositional analysis of timed systems based on over-approximation.
-
TIMES-Pro for
schedulability analysis based on the di-graph real-time task model.
Publications:
For further information on my research, see my
publications (on a separated page).
Last updated:
Last updated: