Topics:

• Multi-Core Architectures
  • Multicore architectures and the multigrid/Gauss-Seidel application, Sverker Holmgren, Wedn., 13.15, March 31, Room 2446.
• Verification
  • S. Burckhardt, R. Alur, and M.M.K. Martin. Checkfence: Checking consistency of concurrent data types on relaxed memory models, ACM Conference on Programming Language Design and Implementation, 2007.
  • Concurrent Executions on Relaxed Memory Models, Rajeev Alur, SPIN07, July 2007
• Scheduling
  • Andersson, B.; Jonsson, J. Preemptive multiprocessor scheduling anomalies. Proc. of Parallel and Distributed Processing Symposium (IPDPS) 2002. processor rate-monotonic scheduling algorithm. It is proven that this algorithm successfully schedules any periodic task system with a worst-case utilization
• Others
  • Gerard J. Holzmann, Dragan Bosnacki: The Design of a Multicore Extension of the SPIN Model Checker. IEEE Trans. Software Eng. 33(10): 659-674 (2007)