[proposed patch for PR target/12081, from http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12081#c19.
 backported to 4.8.0 <mikpe@it.uu.se>]

--- gcc-4.8.0/gcc/config/aarch64/aarch64-builtins.c.~1~	2013-02-28 18:19:33.000000000 +0100
+++ gcc-4.8.0/gcc/config/aarch64/aarch64-builtins.c	2013-05-25 10:28:43.464543731 +0200
@@ -1047,23 +1047,23 @@ aarch64_simd_expand_args (rtx target, in
     switch (argc)
       {
       case 1:
-	pat = GEN_FCN (icode) (target, op[0]);
+	pat = GEN_FCN2 (icode) (target, op[0]);
 	break;
 
       case 2:
-	pat = GEN_FCN (icode) (target, op[0], op[1]);
+	pat = GEN_FCN3 (icode) (target, op[0], op[1]);
 	break;
 
       case 3:
-	pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
+	pat = GEN_FCN4 (icode) (target, op[0], op[1], op[2]);
 	break;
 
       case 4:
-	pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
+	pat = GEN_FCN5 (icode) (target, op[0], op[1], op[2], op[3]);
 	break;
 
       case 5:
-	pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);
+	pat = GEN_FCN6 (icode) (target, op[0], op[1], op[2], op[3], op[4]);
 	break;
 
       default:
@@ -1073,23 +1073,23 @@ aarch64_simd_expand_args (rtx target, in
     switch (argc)
       {
       case 1:
-	pat = GEN_FCN (icode) (op[0]);
+	pat = GEN_FCN1 (icode) (op[0]);
 	break;
 
       case 2:
-	pat = GEN_FCN (icode) (op[0], op[1]);
+	pat = GEN_FCN2 (icode) (op[0], op[1]);
 	break;
 
       case 3:
-	pat = GEN_FCN (icode) (op[0], op[1], op[2]);
+	pat = GEN_FCN3 (icode) (op[0], op[1], op[2]);
 	break;
 
       case 4:
-	pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
+	pat = GEN_FCN4 (icode) (op[0], op[1], op[2], op[3]);
 	break;
 
       case 5:
-	pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
+	pat = GEN_FCN5 (icode) (op[0], op[1], op[2], op[3], op[4]);
 	break;
 
       default:
--- gcc-4.8.0/gcc/config/aarch64/aarch64.c.~1~	2013-03-14 11:48:51.000000000 +0100
+++ gcc-4.8.0/gcc/config/aarch64/aarch64.c	2013-05-25 10:28:43.464543731 +0200
@@ -6693,7 +6693,7 @@ aarch64_expand_vector_init (rtx target,
       x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
       icode = optab_handler (vec_set_optab, mode);
       gcc_assert (icode != CODE_FOR_nothing);
-      emit_insn (GEN_FCN (icode) (target, x, index));
+      emit_insn (GEN_FCN3 (icode) (target, x, index));
       return;
     }
 
--- gcc-4.8.0/gcc/config/alpha/alpha.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/alpha/alpha.c	2013-05-25 10:28:43.464543731 +0200
@@ -6618,16 +6618,16 @@ alpha_expand_builtin (tree exp, rtx targ
   switch (arity)
     {
     case 0:
-      pat = GEN_FCN (icode) (target);
+      pat = GEN_FCN1 (icode) (target);
       break;
     case 1:
       if (nonvoid)
-        pat = GEN_FCN (icode) (target, op[0]);
+        pat = GEN_FCN2 (icode) (target, op[0]);
       else
-	pat = GEN_FCN (icode) (op[0]);
+	pat = GEN_FCN1 (icode) (op[0]);
       break;
     case 2:
-      pat = GEN_FCN (icode) (target, op[0], op[1]);
+      pat = GEN_FCN3 (icode) (target, op[0], op[1]);
       break;
     default:
       gcc_unreachable ();
--- gcc-4.8.0/gcc/config/arm/arm.c.~1~	2013-03-11 12:48:34.000000000 +0100
+++ gcc-4.8.0/gcc/config/arm/arm.c	2013-05-25 10:28:43.464543731 +0200
@@ -21102,7 +21102,7 @@ arm_expand_binop_builtin (enum insn_code
   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
     op1 = copy_to_mode_reg (mode1, op1);
 
-  pat = GEN_FCN (icode) (target, op0, op1);
+  pat = GEN_FCN3 (icode) (target, op0, op1);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -21136,7 +21136,7 @@ arm_expand_unop_builtin (enum insn_code
 	op0 = copy_to_mode_reg (mode0, op0);
     }
 
-  pat = GEN_FCN (icode) (target, op0);
+  pat = GEN_FCN2 (icode) (target, op0);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -21295,23 +21295,23 @@ arm_expand_neon_args (rtx target, int ic
     switch (argc)
       {
       case 1:
-	pat = GEN_FCN (icode) (target, op[0]);
+	pat = GEN_FCN2 (icode) (target, op[0]);
 	break;
 
       case 2:
-	pat = GEN_FCN (icode) (target, op[0], op[1]);
+	pat = GEN_FCN3 (icode) (target, op[0], op[1]);
 	break;
 
       case 3:
-	pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
+	pat = GEN_FCN4 (icode) (target, op[0], op[1], op[2]);
 	break;
 
       case 4:
-	pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
+	pat = GEN_FCN5 (icode) (target, op[0], op[1], op[2], op[3]);
 	break;
 
       case 5:
-	pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);
+	pat = GEN_FCN6 (icode) (target, op[0], op[1], op[2], op[3], op[4]);
 	break;
 
       default:
@@ -21321,23 +21321,23 @@ arm_expand_neon_args (rtx target, int ic
     switch (argc)
       {
       case 1:
-	pat = GEN_FCN (icode) (op[0]);
+	pat = GEN_FCN1 (icode) (op[0]);
 	break;
 
       case 2:
-	pat = GEN_FCN (icode) (op[0], op[1]);
+	pat = GEN_FCN2 (icode) (op[0], op[1]);
 	break;
 
       case 3:
-	pat = GEN_FCN (icode) (op[0], op[1], op[2]);
+	pat = GEN_FCN3 (icode) (op[0], op[1], op[2]);
 	break;
 
       case 4:
-	pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
+	pat = GEN_FCN4 (icode) (op[0], op[1], op[2], op[3]);
 	break;
 
       case 5:
-	pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
+	pat = GEN_FCN5 (icode) (op[0], op[1], op[2], op[3], op[4]);
         break;
 
       default:
@@ -21664,7 +21664,7 @@ arm_expand_builtin (tree exp,
 	  || GET_MODE (target) != tmode
 	  || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
 	target = gen_reg_rtx (tmode);
-      pat = GEN_FCN (icode) (target, op0, op1);
+      pat = GEN_FCN3 (icode) (target, op0, op1);
       if (! pat)
 	return 0;
       emit_insn (pat);
@@ -21712,7 +21712,7 @@ arm_expand_builtin (tree exp,
 	  || GET_MODE (target) != tmode
 	  || !(*insn_data[icode].operand[0].predicate) (target, tmode))
 	target = gen_reg_rtx (tmode);
-      pat = GEN_FCN (icode) (target, op0, op1, op2);
+      pat = GEN_FCN4 (icode) (target, op0, op1, op2);
       if (!pat)
 	return 0;
       emit_insn (pat);
@@ -21771,7 +21771,7 @@ arm_expand_builtin (tree exp,
 	  || GET_MODE (target) != tmode
 	  || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
 	target = gen_reg_rtx (tmode);
-      pat = GEN_FCN (icode) (target, op0, op1, op2);
+      pat = GEN_FCN4 (icode) (target, op0, op1, op2);
       if (! pat)
 	return 0;
       emit_insn (pat);
@@ -21790,7 +21790,7 @@ arm_expand_builtin (tree exp,
       mode0 = insn_data[icode].operand[0].mode;
       if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
         op0 = copy_to_mode_reg (mode0, op0);
-      pat = GEN_FCN (icode) (op0);
+      pat = GEN_FCN1 (icode) (op0);
       if (!pat)
 	return 0;
       emit_insn (pat);
@@ -21809,7 +21809,7 @@ arm_expand_builtin (tree exp,
 	  || GET_MODE (target) != tmode
 	  || !(*insn_data[icode].operand[0].predicate) (target, tmode))
         target = gen_reg_rtx (tmode);
-      pat = GEN_FCN (icode) (target);
+      pat = GEN_FCN1 (icode) (target);
       if (!pat)
         return 0;
       emit_insn (pat);
@@ -21839,7 +21839,7 @@ arm_expand_builtin (tree exp,
 	  || GET_MODE (target) != tmode
 	  || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
 	target = gen_reg_rtx (tmode);
-      pat = GEN_FCN (icode) (target, op0, op1);
+      pat = GEN_FCN3 (icode) (target, op0, op1);
       if (! pat)
 	return 0;
       emit_insn (pat);
@@ -21952,7 +21952,7 @@ arm_expand_builtin (tree exp,
 	  || GET_MODE (target) != tmode
 	  || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
 	target = gen_reg_rtx (tmode);
-      pat = GEN_FCN (icode) (target, op0, op1, op2);
+      pat = GEN_FCN4 (icode) (target, op0, op1, op2);
       if (! pat)
 	return 0;
       emit_insn (pat);
--- gcc-4.8.0/gcc/config/arm/arm.md.~1~	2013-02-22 15:23:12.000000000 +0100
+++ gcc-4.8.0/gcc/config/arm/arm.md	2013-05-25 10:28:43.474543750 +0200
@@ -8833,8 +8833,8 @@ (define_expand "casesi"
     if (!insn_data[(int) code].operand[1].predicate(operands[2], SImode))
       operands[2] = force_reg (SImode, operands[2]);
 
-    emit_jump_insn (GEN_FCN ((int) code) (operands[0], operands[2],
-					  operands[3], operands[4]));
+    emit_jump_insn (GEN_FCN4 ((int) code) (operands[0], operands[2],
+					   operands[3], operands[4]));
     DONE;
   }"
 )
--- gcc-4.8.0/gcc/config/avr/avr.c.~1~	2013-03-12 12:42:26.000000000 +0100
+++ gcc-4.8.0/gcc/config/avr/avr.c	2013-05-25 10:28:43.474543750 +0200
@@ -11724,9 +11724,9 @@ avr_default_expand_builtin (enum insn_co
 
   switch (n_args)
     {
-    case 1: pat = GEN_FCN (icode) (target, xop[0]); break;
-    case 2: pat = GEN_FCN (icode) (target, xop[0], xop[1]); break;
-    case 3: pat = GEN_FCN (icode) (target, xop[0], xop[1], xop[2]); break;
+    case 1: pat = GEN_FCN2 (icode) (target, xop[0]); break;
+    case 2: pat = GEN_FCN3 (icode) (target, xop[0], xop[1]); break;
+    case 3: pat = GEN_FCN4 (icode) (target, xop[0], xop[1], xop[2]); break;
 
     default:
       gcc_unreachable();
@@ -11854,7 +11854,7 @@ avr_expand_builtin (tree exp, rtx target
 
   if (d->n_args == 0)
     {
-      emit_insn ((GEN_FCN (d->icode)) (target));
+      emit_insn ((GEN_FCN1 (d->icode)) (target));
       return NULL_RTX;
     }
 
--- gcc-4.8.0/gcc/config/bfin/bfin.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/bfin/bfin.c	2013-05-25 10:28:43.474543750 +0200
@@ -5359,9 +5359,9 @@ bfin_expand_binop_builtin (enum insn_cod
     op1 = copy_to_mode_reg (mode1, op1);
 
   if (macflag == -1)
-    pat = GEN_FCN (icode) (target, op0, op1);
+    pat = GEN_FCN3 (icode) (target, op0, op1);
   else
-    pat = GEN_FCN (icode) (target, op0, op1, GEN_INT (macflag));
+    pat = GEN_FCN4 (icode) (target, op0, op1, GEN_INT (macflag));
   if (! pat)
     return 0;
 
@@ -5400,7 +5400,7 @@ bfin_expand_unop_builtin (enum insn_code
   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
     op0 = copy_to_mode_reg (mode0, op0);
 
-  pat = GEN_FCN (icode) (target, op0);
+  pat = GEN_FCN2 (icode) (target, op0);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -5459,7 +5459,7 @@ bfin_expand_builtin (tree exp, rtx targe
       if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
 	op0 = copy_to_mode_reg (mode0, op0);
 
-      pat = GEN_FCN (icode) (target, op0, op0);
+      pat = GEN_FCN3 (icode) (target, op0, op0);
       if (! pat)
 	return 0;
       emit_insn (pat);
--- gcc-4.8.0/gcc/config/bfin/bfin.md.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/bfin/bfin.md	2013-05-25 10:28:43.474543750 +0200
@@ -984,10 +984,10 @@ (define_expand "<optab>di3"
   split_di (operands, 3, lo_half, hi_half);
   if (!(*insn_data[icode].operand[2].predicate) (lo_half[2], SImode))
     lo_half[2] = force_reg (SImode, lo_half[2]);
-  emit_insn (GEN_FCN (icode) (lo_half[0], lo_half[1], lo_half[2]));
+  emit_insn (GEN_FCN3 (icode) (lo_half[0], lo_half[1], lo_half[2]));
   if (!(*insn_data[icode].operand[2].predicate) (hi_half[2], SImode))
     hi_half[2] = force_reg (SImode, hi_half[2]);
-  emit_insn (GEN_FCN (icode) (hi_half[0], hi_half[1], hi_half[2]));
+  emit_insn (GEN_FCN3 (icode) (hi_half[0], hi_half[1], hi_half[2]));
   DONE;
 })
 
--- gcc-4.8.0/gcc/config/c6x/c6x.c.~1~	2013-02-26 15:24:17.000000000 +0100
+++ gcc-4.8.0/gcc/config/c6x/c6x.c	2013-05-25 10:28:43.474543750 +0200
@@ -1770,7 +1770,7 @@ c6x_expand_movmem (rtx dst, rtx src, rtx
 	{
 	  enum insn_code icode = (srcmode == SImode ? CODE_FOR_movmisalignsi
 				  : CODE_FOR_movmisaligndi);
-	  emit_insn (GEN_FCN (icode) (reg_lowpart, srcmem));
+	  emit_insn (GEN_FCN2 (icode) (reg_lowpart, srcmem));
 	}
       else
 	emit_move_insn (reg_lowpart, srcmem);
@@ -1804,7 +1804,7 @@ c6x_expand_movmem (rtx dst, rtx src, rtx
 	    {
 	      enum insn_code icode = (dstmode == SImode ? CODE_FOR_movmisalignsi
 				      : CODE_FOR_movmisaligndi);
-	      emit_insn (GEN_FCN (icode) (dstmem, dstreg));
+	      emit_insn (GEN_FCN2 (icode) (dstmem, dstreg));
 	    }
 	  else
 	    emit_move_insn (dstmem, dstreg);
@@ -6585,9 +6585,9 @@ c6x_expand_binop_builtin (enum insn_code
     op1 = copy_to_mode_reg (mode1, op1);
 
   if (match_op)
-    pat = GEN_FCN (icode) (target, target, op0, op1);
+    pat = GEN_FCN4 (icode) (target, target, op0, op1);
   else
-    pat = GEN_FCN (icode) (target, op0, op1);
+    pat = GEN_FCN3 (icode) (target, op0, op1);
 
   if (! pat)
     return 0;
@@ -6628,7 +6628,7 @@ c6x_expand_unop_builtin (enum insn_code
   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
     op0 = copy_to_mode_reg (mode0, op0);
 
-  pat = GEN_FCN (icode) (target, op0);
+  pat = GEN_FCN2 (icode) (target, op0);
   if (! pat)
     return 0;
   emit_insn (pat);
--- gcc-4.8.0/gcc/config/frv/frv.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/frv/frv.c	2013-05-25 10:28:43.474543750 +0200
@@ -8865,7 +8865,7 @@ frv_expand_set_builtin (enum insn_code i
     return NULL_RTX;
 
   target = frv_legitimize_target (icode, target);
-  pat = GEN_FCN (icode) (target, op0);
+  pat = GEN_FCN2 (icode) (target, op0);
   if (! pat)
     return NULL_RTX;
 
@@ -8883,7 +8883,7 @@ frv_expand_unop_builtin (enum insn_code
 
   target = frv_legitimize_target (icode, target);
   op0 = frv_legitimize_argument (icode, 1, op0);
-  pat = GEN_FCN (icode) (target, op0);
+  pat = GEN_FCN2 (icode) (target, op0);
   if (! pat)
     return NULL_RTX;
 
@@ -8903,7 +8903,7 @@ frv_expand_binop_builtin (enum insn_code
   target = frv_legitimize_target (icode, target);
   op0 = frv_legitimize_argument (icode, 1, op0);
   op1 = frv_legitimize_argument (icode, 2, op1);
-  pat = GEN_FCN (icode) (target, op0, op1);
+  pat = GEN_FCN3 (icode) (target, op0, op1);
   if (! pat)
     return NULL_RTX;
 
@@ -8936,7 +8936,7 @@ frv_expand_cut_builtin (enum insn_code i
     op1 = frv_legitimize_argument (icode, 2, op1);
 
   op2 = frv_matching_accg_for_acc (op0);
-  pat = GEN_FCN (icode) (target, op0, op1, op2);
+  pat = GEN_FCN4 (icode) (target, op0, op1, op2);
   if (! pat)
     return NULL_RTX;
 
@@ -8958,7 +8958,7 @@ frv_expand_binopimm_builtin (enum insn_c
 
   target = frv_legitimize_target (icode, target);
   op0 = frv_legitimize_argument (icode, 1, op0);
-  pat = GEN_FCN (icode) (target, op0, op1);
+  pat = GEN_FCN3 (icode) (target, op0, op1);
   if (! pat)
     return NULL_RTX;
 
@@ -8997,7 +8997,7 @@ frv_expand_voidbinop_builtin (enum insn_
 
   op0 = change_address (op0, V4SImode, addr);
   op1 = frv_legitimize_argument (icode, 1, op1);
-  pat = GEN_FCN (icode) (op0, op1);
+  pat = GEN_FCN2 (icode) (op0, op1);
   if (! pat)
     return 0;
 
@@ -9016,7 +9016,7 @@ frv_expand_int_void2arg (enum insn_code
 
   op0 = frv_legitimize_argument (icode, 1, op0);
   op1 = frv_legitimize_argument (icode, 1, op1);
-  pat = GEN_FCN (icode) (op0, op1);
+  pat = GEN_FCN2 (icode) (op0, op1);
   if (! pat)
     return NULL_RTX;
 
@@ -9032,7 +9032,7 @@ frv_expand_prefetches (enum insn_code ic
   rtx pat;
   rtx op0 = frv_read_argument (call, 0);
 
-  pat = GEN_FCN (icode) (force_reg (Pmode, op0));
+  pat = GEN_FCN1 (icode) (force_reg (Pmode, op0));
   if (! pat)
     return 0;
 
@@ -9061,7 +9061,7 @@ frv_expand_voidtriop_builtin (enum insn_
   op1 = frv_legitimize_argument (icode, 1, op1);
   op2 = frv_legitimize_argument (icode, 2, op2);
   op3 = frv_matching_accg_for_acc (op0);
-  pat = GEN_FCN (icode) (op0, op1, op2, op3);
+  pat = GEN_FCN4 (icode) (op0, op1, op2, op3);
   if (! pat)
     return NULL_RTX;
 
@@ -9092,7 +9092,7 @@ frv_expand_voidaccop_builtin (enum insn_
 
   op2 = frv_matching_accg_for_acc (op0);
   op3 = frv_matching_accg_for_acc (op1);
-  pat = GEN_FCN (icode) (op0, op1, op2, op3);
+  pat = GEN_FCN4 (icode) (op0, op1, op2, op3);
   if (! pat)
     return NULL_RTX;
 
@@ -9114,7 +9114,7 @@ frv_expand_load_builtin (enum insn_code
     target = gen_reg_rtx (target_mode);
   op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
   convert_move (target, op0, 1);
-  emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
+  emit_insn (GEN_FCN3 (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
   cfun->machine->has_membar_p = 1;
   return target;
 }
@@ -9130,7 +9130,7 @@ frv_expand_store_builtin (enum insn_code
 
   op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
   convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
-  emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
+  emit_insn (GEN_FCN3 (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
   cfun->machine->has_membar_p = 1;
   return NULL_RTX;
 }
@@ -9165,7 +9165,7 @@ frv_expand_mdpackh_builtin (tree call, r
   emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
   emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
 
-  pat = GEN_FCN (icode) (target, op0, op1);
+  pat = GEN_FCN3 (icode) (target, op0, op1);
   if (! pat)
     return NULL_RTX;
 
@@ -9187,7 +9187,7 @@ frv_expand_mclracc_builtin (tree call)
   if (! op0)
     return NULL_RTX;
 
-  pat = GEN_FCN (icode) (op0);
+  pat = GEN_FCN1 (icode) (op0);
   if (pat)
     emit_insn (pat);
 
@@ -9199,7 +9199,7 @@ frv_expand_mclracc_builtin (tree call)
 static rtx
 frv_expand_noargs_builtin (enum insn_code icode)
 {
-  rtx pat = GEN_FCN (icode) (const0_rtx);
+  rtx pat = GEN_FCN0 (icode) ();
   if (pat)
     emit_insn (pat);
 
@@ -9220,7 +9220,7 @@ frv_expand_mrdacc_builtin (enum insn_cod
   if (! op0)
     return NULL_RTX;
 
-  pat = GEN_FCN (icode) (target, op0);
+  pat = GEN_FCN2 (icode) (target, op0);
   if (! pat)
     return NULL_RTX;
 
@@ -9244,7 +9244,7 @@ frv_expand_mwtacc_builtin (enum insn_cod
     return NULL_RTX;
 
   op1 = frv_legitimize_argument (icode, 1, op1);
-  pat = GEN_FCN (icode) (op0, op1);
+  pat = GEN_FCN2 (icode) (op0, op1);
   if (pat)
     emit_insn (pat);
 
--- gcc-4.8.0/gcc/config/i386/i386.c.~1~	2013-02-21 11:57:10.000000000 +0100
+++ gcc-4.8.0/gcc/config/i386/i386.c	2013-05-25 10:28:43.484543769 +0200
@@ -30030,7 +30030,7 @@ ix86_expand_binop_builtin (enum insn_cod
   if (!insn_data[icode].operand[2].predicate (op1, mode1))
     op1 = copy_to_mode_reg (mode1, op1);
 
-  pat = GEN_FCN (icode) (target, op0, op1);
+  pat = GEN_FCN3 (icode) (target, op0, op1);
   if (! pat)
     return 0;
 
@@ -30235,31 +30235,31 @@ ix86_expand_multi_arg_builtin (enum insn
   switch (nargs)
     {
     case 1:
-      pat = GEN_FCN (icode) (target, args[0].op);
+      pat = GEN_FCN2 (icode) (target, args[0].op);
       break;
 
     case 2:
       if (tf_p)
-	pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
+	pat = GEN_FCN4 (icode) (target, args[0].op, args[1].op,
 			       GEN_INT ((int)sub_code));
       else if (! comparison_p)
-	pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
+	pat = GEN_FCN3 (icode) (target, args[0].op, args[1].op);
       else
 	{
 	  rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
 				       args[0].op,
 				       args[1].op);
 
-	  pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
+	  pat = GEN_FCN4 (icode) (target, cmp_op, args[0].op, args[1].op);
 	}
       break;
 
     case 3:
-      pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
+      pat = GEN_FCN4 (icode) (target, args[0].op, args[1].op, args[2].op);
       break;
 
     case 4:
-      pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op, args[3].op);
+      pat = GEN_FCN5 (icode) (target, args[0].op, args[1].op, args[2].op, args[3].op);
       break;
 
     default:
@@ -30302,7 +30302,7 @@ ix86_expand_unop_vec_merge_builtin (enum
   if (!insn_data[icode].operand[2].predicate (op1, mode0))
     op1 = copy_to_mode_reg (mode0, op1);
 
-  pat = GEN_FCN (icode) (target, op0, op1);
+  pat = GEN_FCN3 (icode) (target, op0, op1);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -30354,7 +30354,7 @@ ix86_expand_sse_compare (const struct bu
     op1 = copy_to_mode_reg (mode1, op1);
 
   op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
-  pat = GEN_FCN (d->icode) (target, op0, op1, op2);
+  pat = GEN_FCN4 (d->icode) (target, op0, op1, op2);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -30401,7 +30401,7 @@ ix86_expand_sse_comi (const struct built
       || !insn_data[d->icode].operand[1].predicate (op1, mode1))
     op1 = copy_to_mode_reg (mode1, op1);
 
-  pat = GEN_FCN (d->icode) (op0, op1);
+  pat = GEN_FCN2 (d->icode) (op0, op1);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -30440,7 +30440,7 @@ ix86_expand_sse_round (const struct buil
 
   op1 = GEN_INT (d->comparison);
 
-  pat = GEN_FCN (d->icode) (target, op0, op1);
+  pat = GEN_FCN3 (d->icode) (target, op0, op1);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -30478,7 +30478,7 @@ ix86_expand_sse_round_vec_pack_sfix (con
 
   op2 = GEN_INT (d->comparison);
 
-  pat = GEN_FCN (d->icode) (target, op0, op1, op2);
+  pat = GEN_FCN4 (d->icode) (target, op0, op1, op2);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -30516,7 +30516,7 @@ ix86_expand_sse_ptest (const struct buil
       || !insn_data[d->icode].operand[1].predicate (op1, mode1))
     op1 = copy_to_mode_reg (mode1, op1);
 
-  pat = GEN_FCN (d->icode) (op0, op1);
+  pat = GEN_FCN2 (d->icode) (op0, op1);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -30587,7 +30587,7 @@ ix86_expand_sse_pcmpestr (const struct b
 
       scratch1 = gen_reg_rtx (tmode1);
 
-      pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
+      pat = GEN_FCN7 (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
     }
   else if (d->code == IX86_BUILTIN_PCMPESTRM128)
     {
@@ -30598,7 +30598,7 @@ ix86_expand_sse_pcmpestr (const struct b
 
       scratch0 = gen_reg_rtx (tmode0);
 
-      pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
+      pat = GEN_FCN7 (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
     }
   else
     {
@@ -30607,7 +30607,7 @@ ix86_expand_sse_pcmpestr (const struct b
       scratch0 = gen_reg_rtx (tmode0);
       scratch1 = gen_reg_rtx (tmode1);
 
-      pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
+      pat = GEN_FCN7 (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
     }
 
   if (! pat)
@@ -30682,7 +30682,7 @@ ix86_expand_sse_pcmpistr (const struct b
 
       scratch1 = gen_reg_rtx (tmode1);
 
-      pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
+      pat = GEN_FCN5 (d->icode) (target, scratch1, op0, op1, op2);
     }
   else if (d->code == IX86_BUILTIN_PCMPISTRM128)
     {
@@ -30693,7 +30693,7 @@ ix86_expand_sse_pcmpistr (const struct b
 
       scratch0 = gen_reg_rtx (tmode0);
 
-      pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
+      pat = GEN_FCN5 (d->icode) (scratch0, target, op0, op1, op2);
     }
   else
     {
@@ -30702,7 +30702,7 @@ ix86_expand_sse_pcmpistr (const struct b
       scratch0 = gen_reg_rtx (tmode0);
       scratch1 = gen_reg_rtx (tmode1);
 
-      pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
+      pat = GEN_FCN5 (d->icode) (scratch0, scratch1, op0, op1, op2);
     }
 
   if (! pat)
@@ -31179,17 +31179,17 @@ ix86_expand_args_builtin (const struct b
   switch (nargs)
     {
     case 1:
-      pat = GEN_FCN (icode) (real_target, args[0].op);
+      pat = GEN_FCN2 (icode) (real_target, args[0].op);
       break;
     case 2:
-      pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
+      pat = GEN_FCN3 (icode) (real_target, args[0].op, args[1].op);
       break;
     case 3:
-      pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
+      pat = GEN_FCN4 (icode) (real_target, args[0].op, args[1].op,
 			     args[2].op);
       break;
     case 4:
-      pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
+      pat = GEN_FCN5 (icode) (real_target, args[0].op, args[1].op,
 			     args[2].op, args[3].op);
       break;
     default:
@@ -31227,7 +31227,7 @@ ix86_expand_special_args_builtin (const
   switch ((enum ix86_builtin_func_type) d->flag)
     {
     case VOID_FTYPE_VOID:
-      emit_insn (GEN_FCN (icode) (target));
+      emit_insn (GEN_FCN1 (icode) (target));
       return 0;
     case VOID_FTYPE_UINT64:
     case VOID_FTYPE_UNSIGNED:
@@ -31398,16 +31398,16 @@ ix86_expand_special_args_builtin (const
   switch (nargs)
     {
     case 0:
-      pat = GEN_FCN (icode) (target);
+      pat = GEN_FCN1 (icode) (target);
       break;
     case 1:
-      pat = GEN_FCN (icode) (target, args[0].op);
+      pat = GEN_FCN2 (icode) (target, args[0].op);
       break;
     case 2:
-      pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
+      pat = GEN_FCN3 (icode) (target, args[0].op, args[1].op);
       break;
     case 3:
-      pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
+      pat = GEN_FCN4 (icode) (target, args[0].op, args[1].op, args[2].op);
       break;
     default:
       gcc_unreachable ();
@@ -31632,7 +31632,7 @@ ix86_expand_builtin (tree exp, rtx targe
 	op1 = copy_to_mode_reg (mode1, op1);
       if (!insn_data[icode].operand[2].predicate (op2, mode2))
 	op2 = copy_to_mode_reg (mode2, op2);
-      pat = GEN_FCN (icode) (op0, op1, op2);
+      pat = GEN_FCN3 (icode) (op0, op1, op2);
       if (! pat)
 	return 0;
       emit_insn (pat);
@@ -31820,7 +31820,7 @@ ix86_expand_builtin (tree exp, rtx targe
 	}
       op0 = gen_rtx_MEM (BLKmode, op0);
 
-      pat = GEN_FCN (icode) (op0);
+      pat = GEN_FCN1 (icode) (op0);
       if (pat)
 	emit_insn (pat);
       return 0;
@@ -31875,7 +31875,7 @@ ix86_expand_builtin (tree exp, rtx targe
 
 	  op2 = gen_lowpart (SImode, op2);
 	  op1 = gen_lowpart (SImode, op1);
-	  pat = GEN_FCN (icode) (op0, op1, op2);
+	  pat = GEN_FCN3 (icode) (op0, op1, op2);
 	}
       else
 	{
@@ -31893,7 +31893,7 @@ ix86_expand_builtin (tree exp, rtx targe
 	    default:
 	      gcc_unreachable ();
 	    }
-	  pat = GEN_FCN (icode) (op0, op1);
+	  pat = GEN_FCN2 (icode) (op0, op1);
 	}
 
       if (pat)
@@ -31937,7 +31937,7 @@ ix86_expand_builtin (tree exp, rtx targe
           unsigned char lsb_index = INTVAL (op1) & 0xFF;
           op1 = GEN_INT (length);
           op2 = GEN_INT (lsb_index);
-          pat = GEN_FCN (icode) (target, op0, op1, op2);
+          pat = GEN_FCN4 (icode) (target, op0, op1, op2);
           if (pat)
             emit_insn (pat);
           return target;
@@ -31959,7 +31959,7 @@ ix86_expand_builtin (tree exp, rtx targe
 
 rdrand_step:
       op0 = gen_reg_rtx (mode0);
-      emit_insn (GEN_FCN (icode) (op0));
+      emit_insn (GEN_FCN1 (icode) (op0));
 
       arg0 = CALL_EXPR_ARG (exp, 0);
       op1 = expand_normal (arg0);
@@ -32009,7 +32009,7 @@ rdrand_step:
 
 rdseed_step:
       op0 = gen_reg_rtx (mode0);
-      emit_insn (GEN_FCN (icode) (op0));
+      emit_insn (GEN_FCN1 (icode) (op0));
 
       arg0 = CALL_EXPR_ARG (exp, 0);
       op1 = expand_normal (arg0);
@@ -32067,7 +32067,7 @@ addcarryx:
 
       op4 = gen_rtx_REG (CCCmode, FLAGS_REG);
       pat = gen_rtx_LTU (VOIDmode, op4, const0_rtx);
-      emit_insn (GEN_FCN (icode) (op0, op2, op3, op4, pat));
+      emit_insn (GEN_FCN5 (icode) (op0, op2, op3, op4, pat));
 
       /* Store the result.  */
       op4 = expand_normal (arg3);
@@ -32279,7 +32279,7 @@ addcarryx:
 	    }
 	}
 
-      pat = GEN_FCN (icode) (subtarget, op0, op1, op2, op3, op4);
+      pat = GEN_FCN6 (icode) (subtarget, op0, op1, op2, op3, op4);
       if (! pat)
 	return const0_rtx;
       emit_insn (pat);
--- gcc-4.8.0/gcc/config/ia64/ia64.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/ia64/ia64.c	2013-05-25 10:28:43.484543769 +0200
@@ -2337,7 +2337,7 @@ ia64_expand_atomic_op (enum rtx_code cod
 	  gcc_unreachable ();
 	}
 
-      emit_insn (GEN_FCN (icode) (old_dst, mem, val));
+      emit_insn (GEN_FCN3 (icode) (old_dst, mem, val));
 
       if (new_dst)
 	{
@@ -2428,7 +2428,7 @@ ia64_expand_atomic_op (enum rtx_code cod
       gcc_unreachable ();
     }
 
-  emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
+  emit_insn (GEN_FCN4 (icode) (cmp_reg, mem, ar_ccv, new_reg));
 
   emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
 }
--- gcc-4.8.0/gcc/config/iq2000/iq2000.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/iq2000/iq2000.c	2013-05-25 10:28:43.484543769 +0200
@@ -2612,30 +2612,30 @@ expand_one_builtin (enum insn_code icode
   switch (argcount)
     {
     case 0:
-	pat = GEN_FCN (icode) (target);
+	pat = GEN_FCN1 (icode) (target);
     case 1:
       if (target)
-	pat = GEN_FCN (icode) (target, op[0]);
+	pat = GEN_FCN2 (icode) (target, op[0]);
       else
-	pat = GEN_FCN (icode) (op[0]);
+	pat = GEN_FCN1 (icode) (op[0]);
       break;
     case 2:
       if (target)
-	pat = GEN_FCN (icode) (target, op[0], op[1]);
+	pat = GEN_FCN3 (icode) (target, op[0], op[1]);
       else
-	pat = GEN_FCN (icode) (op[0], op[1]);
+	pat = GEN_FCN2 (icode) (op[0], op[1]);
       break;
     case 3:
       if (target)
-	pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
+	pat = GEN_FCN4 (icode) (target, op[0], op[1], op[2]);
       else
-	pat = GEN_FCN (icode) (op[0], op[1], op[2]);
+	pat = GEN_FCN3 (icode) (op[0], op[1], op[2]);
       break;
     case 4:
       if (target)
-	pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
+	pat = GEN_FCN5 (icode) (target, op[0], op[1], op[2], op[3]);
       else
-	pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
+	pat = GEN_FCN4 (icode) (op[0], op[1], op[2], op[3]);
       break;
     default:
       gcc_unreachable ();
--- gcc-4.8.0/gcc/config/mep/mep.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/mep/mep.c	2013-05-25 10:28:43.484543769 +0200
@@ -6311,8 +6311,8 @@ mep_expand_builtin (tree exp, rtx target
     }
 
   /* Emit the instruction.  */
-  pat = idata->genfun (op[0], op[1], op[2], op[3], op[4],
-		       op[5], op[6], op[7], op[8], op[9]);
+  pat = idata->genfun.argc10 (op[0], op[1], op[2], op[3], op[4],
+			      op[5], op[6], op[7], op[8], op[9]);
 
   if (GET_CODE (pat) == SET
       && GET_CODE (SET_DEST (pat)) == PC
@@ -7082,9 +7082,9 @@ mep_emit_intrinsic (int intrinsic, const
 	return false;
     }
 
-  emit_insn (idata->genfun (newop[0], newop[1], newop[2],
-			    newop[3], newop[4], newop[5],
-			    newop[6], newop[7], newop[8]));
+  emit_insn (idata->genfun.argc9 (newop[0], newop[1], newop[2],
+				  newop[3], newop[4], newop[5],
+				  newop[6], newop[7], newop[8]));
 
   return true;
 }
--- gcc-4.8.0/gcc/config/picochip/picochip.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/picochip/picochip.c	2013-05-25 10:28:43.484543769 +0200
@@ -55,7 +55,7 @@ along with GCC; see the file COPYING3.
 #include "insn-attr.h"		/* For DFA state_t. */
 #include "insn-config.h"	/* Required by recog.h */
 #include "insn-codes.h"		/* For CODE_FOR_? */
-#include "optabs.h"		/* For GEN_FCN */
+#include "optabs.h"		/* For GEN_FCN? */
 #include "basic-block.h"	/* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
 #include "timevar.h"		/* For TV_SCHED2, in picochip_reorg. */
 #include "libfuncs.h"		/* For memcpy_libfuncs, etc. */
@@ -3941,7 +3941,7 @@ picochip_expand_builtin_2op (enum insn_c
     target = gen_reg_rtx (tmode);
 
   /* Emit and return the new instruction. */
-  pat = GEN_FCN (icode) (target, op0);
+  pat = GEN_FCN2 (icode) (target, op0);
   if (!pat)
     return 0;
   emit_insn (pat);
@@ -3986,7 +3986,7 @@ picochip_expand_builtin_3op (enum insn_c
     target = gen_reg_rtx (tmode);
 
   /* Emit and return the new instruction. */
-  pat = GEN_FCN (icode) (target, op0, op1);
+  pat = GEN_FCN3 (icode) (target, op0, op1);
   if (!pat)
     return 0;
   emit_insn (pat);
@@ -4023,7 +4023,7 @@ picochip_expand_builtin_2opvoid (enum in
     op1 = copy_to_mode_reg (mode1, op1);
 
   /* Emit and return the new instruction. */
-  pat = GEN_FCN (icode) (op0, op1);
+  pat = GEN_FCN2 (icode) (op0, op1);
   if (!pat)
     return 0;
   emit_insn (pat);
--- gcc-4.8.0/gcc/config/rs6000/rs6000.c.~1~	2013-02-08 20:36:04.000000000 +0100
+++ gcc-4.8.0/gcc/config/rs6000/rs6000.c	2013-05-25 10:28:43.494543787 +0200
@@ -9898,7 +9898,7 @@ rs6000_expand_zeroop_builtin (enum insn_
       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
     target = gen_reg_rtx (tmode);
 
-  pat = GEN_FCN (icode) (target);
+  pat = GEN_FCN1 (icode) (target);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -9948,7 +9948,7 @@ rs6000_expand_unop_builtin (enum insn_co
   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
     op0 = copy_to_mode_reg (mode0, op0);
 
-  pat = GEN_FCN (icode) (target, op0);
+  pat = GEN_FCN2 (icode) (target, op0);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -9980,7 +9980,7 @@ altivec_expand_abs_builtin (enum insn_co
   scratch1 = gen_reg_rtx (mode0);
   scratch2 = gen_reg_rtx (mode0);
 
-  pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
+  pat = GEN_FCN4 (icode) (target, op0, scratch1, scratch2);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -10053,7 +10053,7 @@ rs6000_expand_binop_builtin (enum insn_c
   if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
     op1 = copy_to_mode_reg (mode1, op1);
 
-  pat = GEN_FCN (icode) (target, op0, op1);
+  pat = GEN_FCN3 (icode) (target, op0, op1);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -10101,7 +10101,7 @@ altivec_expand_predicate_builtin (enum i
 
   scratch = gen_reg_rtx (mode0);
 
-  pat = GEN_FCN (icode) (scratch, op0, op1);
+  pat = GEN_FCN3 (icode) (scratch, op0, op1);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -10173,7 +10173,7 @@ paired_expand_lv_builtin (enum insn_code
       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
     }
 
-  pat = GEN_FCN (icode) (target, addr);
+  pat = GEN_FCN2 (icode) (target, addr);
 
   if (! pat)
     return 0;
@@ -10219,7 +10219,7 @@ altivec_expand_lv_builtin (enum insn_cod
       addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
     }
 
-  pat = GEN_FCN (icode) (target, addr);
+  pat = GEN_FCN2 (icode) (target, addr);
 
   if (! pat)
     return 0;
@@ -10255,7 +10255,7 @@ spe_expand_stv_builtin (enum insn_code i
   if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
     op2 = copy_to_mode_reg (mode1, op2);
 
-  pat = GEN_FCN (icode) (op1, op2, op0);
+  pat = GEN_FCN3 (icode) (op1, op2, op0);
   if (pat)
     emit_insn (pat);
   return NULL_RTX;
@@ -10296,7 +10296,7 @@ paired_expand_stv_builtin (enum insn_cod
       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
     }
 
-  pat = GEN_FCN (icode) (addr, op0);
+  pat = GEN_FCN2 (icode) (addr, op0);
   if (pat)
     emit_insn (pat);
   return NULL_RTX;
@@ -10338,7 +10338,7 @@ altivec_expand_stv_builtin (enum insn_co
       addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
     }
 
-  pat = GEN_FCN (icode) (addr, op0);
+  pat = GEN_FCN2 (icode) (addr, op0);
   if (pat)
     emit_insn (pat);
   return NULL_RTX;
@@ -10434,9 +10434,9 @@ rs6000_expand_ternop_builtin (enum insn_
     op2 = copy_to_mode_reg (mode2, op2);
 
   if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
-    pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
+    pat = GEN_FCN5 (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
   else 
-    pat = GEN_FCN (icode) (target, op0, op1, op2);
+    pat = GEN_FCN4 (icode) (target, op0, op1, op2);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -10495,7 +10495,7 @@ altivec_expand_ld_builtin (tree exp, rtx
   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
     op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
 
-  pat = GEN_FCN (icode) (target, op0);
+  pat = GEN_FCN2 (icode) (target, op0);
   if (! pat)
     return 0;
   emit_insn (pat);
@@ -10551,7 +10551,7 @@ altivec_expand_st_builtin (tree exp, rtx
   if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
     op1 = copy_to_mode_reg (mode1, op1);
 
-  pat = GEN_FCN (icode) (op0, op1);
+  pat = GEN_FCN2 (icode) (op0, op1);
   if (pat)
     emit_insn (pat);
 
@@ -10608,7 +10608,7 @@ altivec_expand_dst_builtin (tree exp, rt
 	if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
 	  op1 = copy_to_mode_reg (mode1, op1);
 
-	pat = GEN_FCN (d->icode) (op0, op1, op2);
+	pat = GEN_FCN3 (d->icode) (op0, op1, op2);
 	if (pat != 0)
 	  emit_insn (pat);
 
@@ -10804,7 +10804,7 @@ altivec_expand_builtin (tree exp, rtx ta
 	  || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
 	target = gen_reg_rtx (tmode);
 
-      pat = GEN_FCN (icode) (target);
+      pat = GEN_FCN1 (icode) (target);
       if (! pat)
 	return 0;
       emit_insn (pat);
@@ -10823,7 +10823,7 @@ altivec_expand_builtin (tree exp, rtx ta
       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
 	op0 = copy_to_mode_reg (mode0, op0);
 
-      pat = GEN_FCN (icode) (op0);
+      pat = GEN_FCN1 (icode) (op0);
       if (pat)
 	emit_insn (pat);
       return NULL_RTX;
@@ -11130,7 +11130,7 @@ spe_expand_builtin (tree exp, rtx target
 	  || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
 	target = gen_reg_rtx (tmode);
 
-      pat = GEN_FCN (icode) (target);
+      pat = GEN_FCN1 (icode) (target);
       if (! pat)
 	return 0;
       emit_insn (pat);
@@ -11147,7 +11147,7 @@ spe_expand_builtin (tree exp, rtx target
       if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
 	op0 = copy_to_mode_reg (mode0, op0);
 
-      pat = GEN_FCN (icode) (op0);
+      pat = GEN_FCN1 (icode) (op0);
       if (pat)
 	emit_insn (pat);
       return NULL_RTX;
@@ -11197,7 +11197,7 @@ paired_expand_predicate_builtin (enum in
 
   scratch = gen_reg_rtx (CCFPmode);
 
-  pat = GEN_FCN (icode) (scratch, op0, op1);
+  pat = GEN_FCN3 (icode) (scratch, op0, op1);
   if (!pat)
     return const0_rtx;
 
@@ -11270,7 +11270,7 @@ spe_expand_predicate_builtin (enum insn_
 
   scratch = gen_reg_rtx (CCmode);
 
-  pat = GEN_FCN (icode) (scratch, op0, op1);
+  pat = GEN_FCN3 (icode) (scratch, op0, op1);
   if (! pat)
     return const0_rtx;
   emit_insn (pat);
@@ -11376,7 +11376,7 @@ spe_expand_evsel_builtin (enum insn_code
 
   /* Generate the compare.  */
   scratch = gen_reg_rtx (CCmode);
-  pat = GEN_FCN (icode) (scratch, op0, op1);
+  pat = GEN_FCN3 (icode) (scratch, op0, op1);
   if (! pat)
     return const0_rtx;
   emit_insn (pat);
@@ -11537,7 +11537,7 @@ rs6000_expand_builtin (tree exp, rtx tar
 	  target = gen_reg_rtx (tmode);
 
 	/*pat = gen_altivec_lvsr (target, op);*/
-	pat = GEN_FCN (icode) (target, op);
+	pat = GEN_FCN2 (icode) (target, op);
 	if (!pat)
 	  return 0;
 	emit_insn (pat);
@@ -16297,7 +16297,7 @@ rs6000_emit_vector_compare (enum rtx_cod
 	  return NULL_RTX;
 
 	mask = gen_reg_rtx (dmode);
-	emit_insn (GEN_FCN (nor_code) (mask, mask2));
+	emit_insn (GEN_FCN2 (nor_code) (mask, mask2));
 	return mask;
       }
       break;
@@ -16346,7 +16346,7 @@ rs6000_emit_vector_compare (enum rtx_cod
 	  return NULL_RTX;
 
 	mask = gen_reg_rtx (dmode);
-	emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
+	emit_insn (GEN_FCN3 (ior_code) (mask, c_rtx, eq_rtx));
 	return mask;
       }
       break;
@@ -26681,7 +26681,7 @@ rs6000_emit_swdiv_low_precision (rtx dst
   enum machine_mode mode = GET_MODE (dst);
   rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
   enum insn_code code = optab_handler (smul_optab, mode);
-  gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
+  gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN3 (code);
 
   gcc_assert (code != CODE_FOR_nothing);
 
@@ -26752,7 +26752,7 @@ rs6000_emit_swrsqrt (rtx dst, rtx src)
   int i;
   rtx halfthree;
   enum insn_code code = optab_handler (smul_optab, mode);
-  gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
+  gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN3 (code);
 
   gcc_assert (code != CODE_FOR_nothing);
 
@@ -27069,7 +27069,7 @@ altivec_expand_vec_perm_const (rtx opera
 	    x = target;
 	  else
 	    x = gen_reg_rtx (omode);
-	  emit_insn (GEN_FCN (icode) (x, op0, op1));
+	  emit_insn (GEN_FCN3 (icode) (x, op0, op1));
 	  if (omode != V16QImode)
 	    emit_move_insn (target, gen_lowpart (V16QImode, x));
 	  return true;
--- gcc-4.8.0/gcc/config/sh/sh.c.~1~	2013-03-13 19:09:10.000000000 +0100
+++ gcc-4.8.0/gcc/config/sh/sh.c	2013-05-25 10:28:43.494543787 +0200
@@ -11999,16 +11999,16 @@ sh_expand_builtin (tree exp, rtx target,
   switch (nop)
     {
     case 1:
-      pat = (*insn_data[d->icode].genfun) (op[0]);
+      pat = GEN_FCN1 (d->icode) (op[0]);
       break;
     case 2:
-      pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
+      pat = GEN_FCN2 (d->icode) (op[0], op[1]);
       break;
     case 3:
-      pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
+      pat = GEN_FCN3 (d->icode) (op[0], op[1], op[2]);
       break;
     case 4:
-      pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
+      pat = GEN_FCN4 (d->icode) (op[0], op[1], op[2], op[3]);
       break;
     default:
       gcc_unreachable ();
--- gcc-4.8.0/gcc/config/sparc/sparc.c.~1~	2013-01-30 10:26:21.000000000 +0100
+++ gcc-4.8.0/gcc/config/sparc/sparc.c	2013-05-25 10:28:43.494543787 +0200
@@ -10146,19 +10146,19 @@ sparc_expand_builtin (tree exp, rtx targ
   switch (arg_count)
     {
     case 0:
-      pat = GEN_FCN (icode) (op[0]);
+      pat = GEN_FCN1 (icode) (op[0]);
       break;
     case 1:
       if (nonvoid)
-	pat = GEN_FCN (icode) (op[0], op[1]);
+	pat = GEN_FCN2 (icode) (op[0], op[1]);
       else
-	pat = GEN_FCN (icode) (op[1]);
+	pat = GEN_FCN1 (icode) (op[1]);
       break;
     case 2:
-      pat = GEN_FCN (icode) (op[0], op[1], op[2]);
+      pat = GEN_FCN3 (icode) (op[0], op[1], op[2]);
       break;
     case 3:
-      pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
+      pat = GEN_FCN4 (icode) (op[0], op[1], op[2], op[3]);
       break;
     default:
       gcc_unreachable ();
--- gcc-4.8.0/gcc/config/spu/spu.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/spu/spu.c	2013-05-25 10:28:43.494543787 +0200
@@ -878,7 +878,7 @@ spu_emit_branch_or_set (int is_set, rtx
       if (!(*insn_data[spu_comp_icode[index][scode]].operand[2].predicate)
 	  (op1, op_mode))
 	op1 = force_reg (op_mode, op1);
-      comp_rtx = GEN_FCN (spu_comp_icode[index][scode]) (compare_result,
+      comp_rtx = GEN_FCN3 (spu_comp_icode[index][scode]) (compare_result,
 							 op0, op1);
       if (comp_rtx == 0)
 	abort ();
@@ -887,14 +887,14 @@ spu_emit_branch_or_set (int is_set, rtx
       if (eq_test)
         {
           eq_result = gen_reg_rtx (comp_mode);
-          eq_rtx = GEN_FCN (spu_comp_icode[index][eq_code]) (eq_result,
+          eq_rtx = GEN_FCN3 (spu_comp_icode[index][eq_code]) (eq_result,
 							     op0, op1);
           if (eq_rtx == 0)
 	    abort ();
           emit_insn (eq_rtx);
           ior_code = optab_handler (ior_optab, comp_mode);
           gcc_assert (ior_code != CODE_FOR_nothing);
-          emit_insn (GEN_FCN (ior_code)
+          emit_insn (GEN_FCN3 (ior_code)
 		     (compare_result, compare_result, eq_result));
         }
     }
@@ -4446,7 +4446,7 @@ spu_expand_mov (rtx * ops, enum machine_
 	{
 	  enum insn_code icode = convert_optab_handler (trunc_optab,
 							mode, imode);
-	  emit_insn (GEN_FCN (icode) (ops[0], from));
+	  emit_insn (GEN_FCN2 (icode) (ops[0], from));
 	}
       else
 	emit_insn (gen_extend_insn (ops[0], from, mode, imode, 1));
@@ -6146,7 +6146,7 @@ spu_emit_vector_compare (enum rtx_code r
 
             nor_code = optab_handler (one_cmpl_optab, dest_mode);
             gcc_assert (nor_code != CODE_FOR_nothing);
-            emit_insn (GEN_FCN (nor_code) (mask, rev_mask));
+            emit_insn (GEN_FCN2 (nor_code) (mask, rev_mask));
             if (dmode != dest_mode)
               {
                 rtx temp = gen_reg_rtx (dest_mode);
@@ -6181,7 +6181,7 @@ spu_emit_vector_compare (enum rtx_code r
 
             ior_code = optab_handler (ior_optab, dest_mode);
             gcc_assert (ior_code != CODE_FOR_nothing);
-            emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
+            emit_insn (GEN_FCN3 (ior_code) (mask, c_rtx, eq_rtx));
             if (dmode != dest_mode)
               {
                 rtx temp = gen_reg_rtx (dest_mode);
@@ -6202,7 +6202,7 @@ spu_emit_vector_compare (enum rtx_code r
 
             ior_code = optab_handler (ior_optab, dest_mode);
             gcc_assert (ior_code != CODE_FOR_nothing);
-            emit_insn (GEN_FCN (ior_code) (mask, lt_rtx, gt_rtx));
+            emit_insn (GEN_FCN3 (ior_code) (mask, lt_rtx, gt_rtx));
             if (dmode != dest_mode)
               {
                 rtx temp = gen_reg_rtx (dest_mode);
@@ -6223,7 +6223,7 @@ spu_emit_vector_compare (enum rtx_code r
 
             and_code = optab_handler (and_optab, dest_mode);
             gcc_assert (and_code != CODE_FOR_nothing);
-            emit_insn (GEN_FCN (and_code) (mask, a_rtx, b_rtx));
+            emit_insn (GEN_FCN3 (and_code) (mask, a_rtx, b_rtx));
             if (dmode != dest_mode)
               {
                 rtx temp = gen_reg_rtx (dest_mode);
@@ -6252,7 +6252,7 @@ spu_emit_vector_compare (enum rtx_code r
         }
     }
 
-  emit_insn (GEN_FCN (vec_cmp_insn) (mask, op0, op1));
+  emit_insn (GEN_FCN3 (vec_cmp_insn) (mask, op0, op1));
   if (dmode != dest_mode)
     {
       rtx temp = gen_reg_rtx (dest_mode);
@@ -6456,7 +6456,7 @@ spu_expand_builtin_1 (struct spu_builtin
                  gen_rtx_NEG (GET_MODE (addr), addr)));
       op = gen_rtx_MEM (mode, op);
 
-      pat = GEN_FCN (icode) (target, op);
+      pat = GEN_FCN2 (icode) (target, op);
       if (!pat) 
         return 0;
       emit_insn (pat);
@@ -6512,25 +6512,25 @@ spu_expand_builtin_1 (struct spu_builtin
   switch (n_operands)
     {
     case 0:
-      pat = GEN_FCN (icode) (0);
+      pat = GEN_FCN0 (icode) ();
       break;
     case 1:
-      pat = GEN_FCN (icode) (ops[0]);
+      pat = GEN_FCN1 (icode) (ops[0]);
       break;
     case 2:
-      pat = GEN_FCN (icode) (ops[0], ops[1]);
+      pat = GEN_FCN2 (icode) (ops[0], ops[1]);
       break;
     case 3:
-      pat = GEN_FCN (icode) (ops[0], ops[1], ops[2]);
+      pat = GEN_FCN3 (icode) (ops[0], ops[1], ops[2]);
       break;
     case 4:
-      pat = GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]);
+      pat = GEN_FCN4 (icode) (ops[0], ops[1], ops[2], ops[3]);
       break;
     case 5:
-      pat = GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3], ops[4]);
+      pat = GEN_FCN5 (icode) (ops[0], ops[1], ops[2], ops[3], ops[4]);
       break;
     case 6:
-      pat = GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3], ops[4], ops[5]);
+      pat = GEN_FCN6 (icode) (ops[0], ops[1], ops[2], ops[3], ops[4], ops[5]);
       break;
     default:
       abort ();
--- gcc-4.8.0/gcc/config/stormy16/stormy16.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/config/stormy16/stormy16.c	2013-05-25 10:28:43.494543787 +0200
@@ -2354,8 +2354,8 @@ xstormy16_expand_builtin (tree exp, rtx
 	retval = op[o];
     }
 
-  pat = GEN_FCN (code) (op[0], op[1], op[2], op[3], op[4],
-			op[5], op[6], op[7], op[8], op[9]);
+  pat = GEN_FCN10 (code) (op[0], op[1], op[2], op[3], op[4],
+			  op[5], op[6], op[7], op[8], op[9]);
   emit_insn (pat);
 
   for (o = 0; s16builtins[i].arg_ops[o]; o++)
--- gcc-4.8.0/gcc/config/tilegx/tilegx.c.~1~	2013-02-26 15:34:26.000000000 +0100
+++ gcc-4.8.0/gcc/config/tilegx/tilegx.c	2013-05-25 10:28:43.494543787 +0200
@@ -2062,7 +2062,7 @@ tilegx_expand_constant_multiply_given_se
 	  gcc_assert (shift_count > 0 && shift_count < 64);
 
 	  /* Emit the actual instruction.  */
-	  emit_insn (GEN_FCN (opcode)
+	  emit_insn (GEN_FCN3 (opcode)
 		     (out, subexprs[entry->lhs],
 		      gen_rtx_CONST_INT (DImode, shift_count)));
 	}
@@ -2076,7 +2076,7 @@ tilegx_expand_constant_multiply_given_se
 	  gcc_assert (entry->rhs < num_subexprs);
 
 	  /* Emit the actual instruction.  */
-	  emit_insn (GEN_FCN (opcode)
+	  emit_insn (GEN_FCN3 (opcode)
 		     (out, subexprs[entry->lhs], subexprs[entry->rhs]));
 	}
 
@@ -3442,7 +3442,6 @@ tilegx_expand_builtin (tree exp,
   rtx op[MAX_BUILTIN_ARGS + 1], pat;
   int opnum;
   bool nonvoid;
-  insn_gen_fn fn;
 
   if (fcode >= TILEGX_BUILTIN_max)
     internal_error ("bad builtin fcode");
@@ -3513,26 +3512,25 @@ tilegx_expand_builtin (tree exp,
       op[0] = target;
     }
 
-  fn = GEN_FCN (icode);
   switch (opnum)
     {
     case 0:
-      pat = fn (NULL_RTX);
+      pat = GEN_FCN0 (icode) ();
       break;
     case 1:
-      pat = fn (op[0]);
+      pat = GEN_FCN1 (icode) (op[0]);
       break;
     case 2:
-      pat = fn (op[0], op[1]);
+      pat = GEN_FCN2 (icode) (op[0], op[1]);
       break;
     case 3:
-      pat = fn (op[0], op[1], op[2]);
+      pat = GEN_FCN3 (icode) (op[0], op[1], op[2]);
       break;
     case 4:
-      pat = fn (op[0], op[1], op[2], op[3]);
+      pat = GEN_FCN4 (icode) (op[0], op[1], op[2], op[3]);
       break;
     case 5:
-      pat = fn (op[0], op[1], op[2], op[3], op[4]);
+      pat = GEN_FCN5 (icode) (op[0], op[1], op[2], op[3], op[4]);
       break;
     default:
       gcc_unreachable ();
--- gcc-4.8.0/gcc/config/tilepro/tilepro.c.~1~	2013-02-26 15:34:26.000000000 +0100
+++ gcc-4.8.0/gcc/config/tilepro/tilepro.c	2013-05-25 10:28:43.494543787 +0200
@@ -1895,7 +1895,7 @@ tilepro_expand_constant_multiply_given_s
 	  gcc_assert (shift_count > 0 && shift_count < 32);
 
 	  /* Emit the actual instruction.  */
-	  emit_insn (GEN_FCN (opcode)
+	  emit_insn (GEN_FCN3 (opcode)
 		     (out, subexprs[entry->lhs],
 		      gen_rtx_CONST_INT (SImode, shift_count)));
 	}
@@ -1909,7 +1909,7 @@ tilepro_expand_constant_multiply_given_s
 	  gcc_assert (entry->rhs < num_subexprs);
 
 	  /* Emit the actual instruction.  */
-	  emit_insn (GEN_FCN (opcode)
+	  emit_insn (GEN_FCN3 (opcode)
 		     (out, subexprs[entry->lhs], subexprs[entry->rhs]));
 	}
 
@@ -3092,7 +3092,6 @@ tilepro_expand_builtin (tree exp,
   rtx op[MAX_BUILTIN_ARGS + 1], pat;
   int opnum;
   bool nonvoid;
-  insn_gen_fn fn;
 
   if (fcode >= TILEPRO_BUILTIN_max)
     internal_error ("bad builtin fcode");
@@ -3141,26 +3140,25 @@ tilepro_expand_builtin (tree exp,
       op[0] = target;
     }
 
-  fn = GEN_FCN (icode);
   switch (opnum)
     {
     case 0:
-      pat = fn (NULL_RTX);
+      pat = GEN_FCN0 ();
       break;
     case 1:
-      pat = fn (op[0]);
+      pat = GEN_FCN1 (op[0]);
       break;
     case 2:
-      pat = fn (op[0], op[1]);
+      pat = GEN_FCN2 (op[0], op[1]);
       break;
     case 3:
-      pat = fn (op[0], op[1], op[2]);
+      pat = GEN_FCN3 (op[0], op[1], op[2]);
       break;
     case 4:
-      pat = fn (op[0], op[1], op[2], op[3]);
+      pat = GEN_FCN4 (op[0], op[1], op[2], op[3]);
       break;
     case 5:
-      pat = fn (op[0], op[1], op[2], op[3], op[4]);
+      pat = GEN_FCN5 (op[0], op[1], op[2], op[3], op[4]);
       break;
     default:
       gcc_unreachable ();
--- gcc-4.8.0/gcc/expr.c.~1~	2013-03-06 18:18:46.000000000 +0100
+++ gcc-4.8.0/gcc/expr.c	2013-05-25 10:28:43.494543787 +0200
@@ -119,7 +119,7 @@ struct store_by_pieces_d
   int reverse;
 };
 
-static void move_by_pieces_1 (rtx (*) (rtx, ...), enum machine_mode,
+static void move_by_pieces_1 (rtx (*) (rtx, rtx), enum machine_mode,
 			      struct move_by_pieces_d *);
 static bool block_move_libcall_safe_for_call_parm (void);
 static bool emit_block_move_via_movmem (rtx, rtx, rtx, unsigned, unsigned, HOST_WIDE_INT);
@@ -128,7 +128,7 @@ static void emit_block_move_via_loop (rt
 static rtx clear_by_pieces_1 (void *, HOST_WIDE_INT, enum machine_mode);
 static void clear_by_pieces (rtx, unsigned HOST_WIDE_INT, unsigned int);
 static void store_by_pieces_1 (struct store_by_pieces_d *, unsigned int);
-static void store_by_pieces_2 (rtx (*) (rtx, ...), enum machine_mode,
+static void store_by_pieces_2 (rtx (*) (rtx, rtx), enum machine_mode,
 			       struct store_by_pieces_d *);
 static tree clear_storage_libcall_fn (int);
 static rtx compress_float_constant (rtx, rtx);
@@ -966,7 +966,7 @@ move_by_pieces (rtx to, rtx from, unsign
 
       icode = optab_handler (mov_optab, mode);
       if (icode != CODE_FOR_nothing && align >= GET_MODE_ALIGNMENT (mode))
-	move_by_pieces_1 (GEN_FCN (icode), mode, &data);
+	move_by_pieces_1 (GEN_FCN2 (icode), mode, &data);
 
       max_size = GET_MODE_SIZE (mode);
     }
@@ -1043,7 +1043,7 @@ move_by_pieces_ninsns (unsigned HOST_WID
    to make a move insn for that mode.  DATA has all the other info.  */
 
 static void
-move_by_pieces_1 (rtx (*genfun) (rtx, ...), enum machine_mode mode,
+move_by_pieces_1 (rtx (*genfun) (rtx, rtx), enum machine_mode mode,
 		  struct move_by_pieces_d *data)
 {
   unsigned int size = GET_MODE_SIZE (mode);
@@ -2643,7 +2643,7 @@ store_by_pieces_1 (struct store_by_piece
 
       icode = optab_handler (mov_optab, mode);
       if (icode != CODE_FOR_nothing && align >= GET_MODE_ALIGNMENT (mode))
-	store_by_pieces_2 (GEN_FCN (icode), mode, data);
+	store_by_pieces_2 (GEN_FCN2 (icode), mode, data);
 
       max_size = GET_MODE_SIZE (mode);
     }
@@ -2657,7 +2657,7 @@ store_by_pieces_1 (struct store_by_piece
    to make a move insn for that mode.  DATA has all the other info.  */
 
 static void
-store_by_pieces_2 (rtx (*genfun) (rtx, ...), enum machine_mode mode,
+store_by_pieces_2 (rtx (*genfun) (rtx, rtx), enum machine_mode mode,
 		   struct store_by_pieces_d *data)
 {
   unsigned int size = GET_MODE_SIZE (mode);
@@ -3096,7 +3096,7 @@ emit_move_via_integer (enum machine_mode
   y = emit_move_change_mode (imode, mode, y, force);
   if (y == NULL_RTX)
     return NULL_RTX;
-  return emit_insn (GEN_FCN (code) (x, y));
+  return emit_insn (GEN_FCN2 (code) (x, y));
 }
 
 /* A subroutine of emit_move_insn_1.  X is a push_operand in MODE.
@@ -3292,7 +3292,7 @@ emit_move_ccmode (enum machine_mode mode
 	{
 	  x = emit_move_change_mode (CCmode, mode, x, true);
 	  y = emit_move_change_mode (CCmode, mode, y, true);
-	  return emit_insn (GEN_FCN (code) (x, y));
+	  return emit_insn (GEN_FCN2 (code) (x, y));
 	}
     }
 
@@ -3429,7 +3429,7 @@ emit_move_insn_1 (rtx x, rtx y)
 
   code = optab_handler (mov_optab, mode);
   if (code != CODE_FOR_nothing)
-    return emit_insn (GEN_FCN (code) (x, y));
+    return emit_insn (GEN_FCN2 (code) (x, y));
 
   /* Expand complex moves by moving real part and imag part.  */
   if (COMPLEX_MODE_P (mode))
@@ -6322,7 +6322,7 @@ store_constructor (tree exp, rtx target,
 	  }
 
 	if (vector)
-	  emit_insn (GEN_FCN (icode)
+	  emit_insn (GEN_FCN2 (icode)
 		     (target,
 		      gen_rtx_PARALLEL (GET_MODE (target), vector)));
 	break;
@@ -10359,7 +10359,7 @@ expand_expr_real_1 (tree exp, rtx target
 	      reg = gen_reg_rtx (mode);
 
 	      /* Nor can the insn generator.  */
-	      insn = GEN_FCN (icode) (reg, op0);
+	      insn = GEN_FCN2 (icode) (reg, op0);
 	      emit_insn (insn);
 	      return reg;
 	    }
--- gcc-4.8.0/gcc/genoutput.c.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/genoutput.c	2013-05-25 10:28:43.494543787 +0200
@@ -404,9 +404,25 @@ output_insn_data (void)
 	}
 
       if (d->name && d->name[0] != '*')
-	printf ("    (insn_gen_fn) gen_%s,\n", d->name);
+	{
+	  int i;
+
+	  printf ("#if HAVE_DESIGNATED_UNION_INITIALIZERS\n");
+	  printf ("    { .argc%d = gen_%s },\n", d->n_generator_args, d->name);
+	  printf ("#else\n");
+	  printf ("    { ");
+	  for (i = 0; i < d->n_generator_args; i++)
+	    printf ("0, ");
+	  printf ("gen_%s, ", d->name);
+	  for (i = d->n_generator_args + 1; i <= 11; i++)
+	    printf ("0, ");
+	  printf ("},\n");
+	  printf ("#endif\n");
+	}
       else
-	printf ("    0,\n");
+	{
+	  printf ("    { 0 },\n");
+	}
 
       printf ("    &operand_data[%d],\n", d->operand_number);
       printf ("    %d,\n", d->n_generator_args);
--- gcc-4.8.0/gcc/lra-constraints.c.~1~	2013-02-22 17:30:22.000000000 +0100
+++ gcc-4.8.0/gcc/lra-constraints.c	2013-05-25 10:28:43.494543787 +0200
@@ -997,7 +997,7 @@ check_and_process_move (bool *change_p,
       scratch_reg = (lra_create_new_reg_with_unique_value
 		     (insn_data[sri.icode].operand[2].mode, NULL_RTX,
 		      scratch_class, "scratch"));
-      emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
+      emit_insn (GEN_FCN3 (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
 				      sreg, scratch_reg));
     }
   before = get_insns ();
--- gcc-4.8.0/gcc/optabs.c.~1~	2013-03-09 08:54:02.000000000 +0100
+++ gcc-4.8.0/gcc/optabs.c	2013-05-25 10:28:43.504543806 +0200
@@ -792,7 +792,7 @@ expand_vector_broadcast (enum machine_mo
     return NULL;
 
   ret = gen_reg_rtx (vmode);
-  emit_insn (GEN_FCN (icode) (ret, gen_rtx_PARALLEL (vmode, vec)));
+  emit_insn (GEN_FCN2 (icode) (ret, gen_rtx_PARALLEL (vmode, vec)));
 
   return ret;
 }
@@ -4098,7 +4098,7 @@ prepare_cmp_insn (rtx x, rtx y, enum rtx
 	  result_mode = insn_data[cmp_code].operand[0].mode;
 	  result = gen_reg_rtx (result_mode);
 	  size = convert_to_mode (cmp_mode, size, 1);
-	  emit_insn (GEN_FCN (cmp_code) (result, x, y, size, opalign));
+	  emit_insn (GEN_FCN5 (cmp_code) (result, x, y, size, opalign));
 
           *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, result, const0_rtx);
           *pmode = result_mode;
@@ -4275,7 +4275,7 @@ emit_cmp_and_jump_insn_1 (rtx test, enum
 
   gcc_assert (icode != CODE_FOR_nothing);
   gcc_assert (insn_operand_matches (icode, 0, test));
-  insn = emit_jump_insn (GEN_FCN (icode) (test, XEXP (test, 0),
+  insn = emit_jump_insn (GEN_FCN4 (icode) (test, XEXP (test, 0),
                                           XEXP (test, 1), label));
   if (prob != -1
       && profile_status != PROFILE_ABSENT
@@ -4704,7 +4704,7 @@ gen_add2_insn (rtx x, rtx y)
   gcc_assert (insn_operand_matches (icode, 1, x));
   gcc_assert (insn_operand_matches (icode, 2, y));
 
-  return GEN_FCN (icode) (x, x, y);
+  return GEN_FCN3 (icode) (x, x, y);
 }
 
 /* Generate and return an insn body to add r1 and c,
@@ -4721,7 +4721,7 @@ gen_add3_insn (rtx r0, rtx r1, rtx c)
       || !insn_operand_matches (icode, 2, c))
     return NULL_RTX;
 
-  return GEN_FCN (icode) (r0, r1, c);
+  return GEN_FCN3 (icode) (r0, r1, c);
 }
 
 int
@@ -4755,7 +4755,7 @@ gen_sub2_insn (rtx x, rtx y)
   gcc_assert (insn_operand_matches (icode, 1, x));
   gcc_assert (insn_operand_matches (icode, 2, y));
 
-  return GEN_FCN (icode) (x, x, y);
+  return GEN_FCN3 (icode) (x, x, y);
 }
 
 /* Generate and return an insn body to subtract r1 and c,
@@ -4772,7 +4772,7 @@ gen_sub3_insn (rtx r0, rtx r1, rtx c)
       || !insn_operand_matches (icode, 2, c))
     return NULL_RTX;
 
-  return GEN_FCN (icode) (r0, r1, c);
+  return GEN_FCN3 (icode) (r0, r1, c);
 }
 
 int
@@ -4836,7 +4836,7 @@ gen_extend_insn (rtx x, rtx y, enum mach
 		 enum machine_mode mfrom, int unsignedp)
 {
   enum insn_code icode = can_extend_p (mto, mfrom, unsignedp);
-  return GEN_FCN (icode) (x, y);
+  return GEN_FCN2 (icode) (x, y);
 }
 
 /* can_fix_p and can_float_p say whether the target machine
@@ -6367,7 +6367,7 @@ gen_cond_trap (enum rtx_code code, rtx o
   if (!trap_rtx)
     insn = NULL_RTX;
   else
-    insn = GEN_FCN (icode) (trap_rtx, XEXP (trap_rtx, 0), XEXP (trap_rtx, 1),
+    insn = GEN_FCN4 (icode) (trap_rtx, XEXP (trap_rtx, 0), XEXP (trap_rtx, 1),
 			    tcode);
 
   /* If that failed, then give up.  */
@@ -8206,28 +8206,28 @@ maybe_gen_insn (enum insn_code icode, un
   switch (nops)
     {
     case 1:
-      return GEN_FCN (icode) (ops[0].value);
+      return GEN_FCN1 (icode) (ops[0].value);
     case 2:
-      return GEN_FCN (icode) (ops[0].value, ops[1].value);
+      return GEN_FCN2 (icode) (ops[0].value, ops[1].value);
     case 3:
-      return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value);
+      return GEN_FCN3 (icode) (ops[0].value, ops[1].value, ops[2].value);
     case 4:
-      return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
-			      ops[3].value);
+      return GEN_FCN4 (icode) (ops[0].value, ops[1].value, ops[2].value,
+			       ops[3].value);
     case 5:
-      return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
-			      ops[3].value, ops[4].value);
+      return GEN_FCN5 (icode) (ops[0].value, ops[1].value, ops[2].value,
+			       ops[3].value, ops[4].value);
     case 6:
-      return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
-			      ops[3].value, ops[4].value, ops[5].value);
+      return GEN_FCN6 (icode) (ops[0].value, ops[1].value, ops[2].value,
+			       ops[3].value, ops[4].value, ops[5].value);
     case 7:
-      return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
-			      ops[3].value, ops[4].value, ops[5].value,
-			      ops[6].value);
+      return GEN_FCN7 (icode) (ops[0].value, ops[1].value, ops[2].value,
+			       ops[3].value, ops[4].value, ops[5].value,
+			       ops[6].value);
     case 8:
-      return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
-			      ops[3].value, ops[4].value, ops[5].value,
-			      ops[6].value, ops[7].value);
+      return GEN_FCN8 (icode) (ops[0].value, ops[1].value, ops[2].value,
+			       ops[3].value, ops[4].value, ops[5].value,
+			       ops[6].value, ops[7].value);
     }
   gcc_unreachable ();
 }
--- gcc-4.8.0/gcc/optabs.h.~1~	2013-02-19 01:04:49.000000000 +0100
+++ gcc-4.8.0/gcc/optabs.h	2013-05-25 10:28:43.504543806 +0200
@@ -44,7 +44,18 @@ struct convert_optab_libcall_d
 
 /* Given an enum insn_code, access the function to construct
    the body of that kind of insn.  */
-#define GEN_FCN(CODE) (insn_data[CODE].genfun)
+#define GEN_FCN0(CODE)	(insn_data[CODE].genfun.argc0)
+#define GEN_FCN1(CODE)	(insn_data[CODE].genfun.argc1)
+#define GEN_FCN2(CODE)	(insn_data[CODE].genfun.argc2)
+#define GEN_FCN3(CODE)	(insn_data[CODE].genfun.argc3)
+#define GEN_FCN4(CODE)	(insn_data[CODE].genfun.argc4)
+#define GEN_FCN5(CODE)	(insn_data[CODE].genfun.argc5)
+#define GEN_FCN6(CODE)	(insn_data[CODE].genfun.argc6)
+#define GEN_FCN7(CODE)	(insn_data[CODE].genfun.argc7)
+#define GEN_FCN8(CODE)	(insn_data[CODE].genfun.argc8)
+#define GEN_FCN9(CODE)	(insn_data[CODE].genfun.argc9)
+#define GEN_FCN10(CODE)	(insn_data[CODE].genfun.argc10)
+#define GEN_FCN11(CODE)	(insn_data[CODE].genfun.argc11)
 
 /* Contains the optab used for each rtx code, and vice-versa.  */
 extern const optab code_to_optab_[NUM_RTX_CODE];
--- gcc-4.8.0/gcc/recog.h.~1~	2013-01-10 21:38:27.000000000 +0100
+++ gcc-4.8.0/gcc/recog.h	2013-05-25 10:28:43.504543806 +0200
@@ -256,7 +256,6 @@ extern struct operand_alternative recog_
 
 typedef int (*insn_operand_predicate_fn) (rtx, enum machine_mode);
 typedef const char * (*insn_output_fn) (rtx *, rtx);
-typedef rtx (*insn_gen_fn) (rtx, ...);
 
 struct insn_operand_data
 {
@@ -291,14 +290,41 @@ struct insn_data_d
     const char *const *multi;
     insn_output_fn function;
   } output;
+  union {
+    rtx (*argc0)	(void);
+    rtx (*argc1)	(rtx);
+    rtx (*argc2)	(rtx, rtx);
+    rtx (*argc3)	(rtx, rtx, rtx);
+    rtx (*argc4)	(rtx, rtx, rtx, rtx);
+    rtx (*argc5)	(rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc6)	(rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc7)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc8)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc9)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc10)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc11)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+  } genfun;
 #else
   struct {
     const char *single;
     const char *const *multi;
     insn_output_fn function;
   } output;
+  struct {
+    rtx (*argc0)	(void);
+    rtx (*argc1)	(rtx);
+    rtx (*argc2)	(rtx, rtx);
+    rtx (*argc3)	(rtx, rtx, rtx);
+    rtx (*argc4)	(rtx, rtx, rtx, rtx);
+    rtx (*argc5)	(rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc6)	(rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc7)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc8)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc9)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc10)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+    rtx (*argc11)	(rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx);
+  } genfun;
 #endif
-  const insn_gen_fn genfun;
   const struct insn_operand_data *const operand;
 
   const char n_generator_args;
--- gcc-4.8.0/gcc/reload1.c.~1~	2013-01-21 15:55:05.000000000 +0100
+++ gcc-4.8.0/gcc/reload1.c	2013-05-25 10:28:43.504543806 +0200
@@ -7538,7 +7538,7 @@ emit_input_reload_insns (struct insn_cha
 	      /* We'd have to add extra code to handle this case.  */
 	      gcc_assert (!third_reload_reg);
 
-	      emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
+	      emit_insn (GEN_FCN3 (icode) (reloadreg, real_oldequiv,
 					  second_reload_reg));
 	      special = 1;
 	    }
@@ -7548,7 +7548,7 @@ emit_input_reload_insns (struct insn_cha
 		 intermediate register (a tertiary reload).  */
 	      if (tertiary_icode != CODE_FOR_nothing)
 		{
-		  emit_insn ((GEN_FCN (tertiary_icode)
+		  emit_insn ((GEN_FCN3 (tertiary_icode)
 			      (second_reload_reg, real_oldequiv,
 			       third_reload_reg)));
 		}
@@ -7657,7 +7657,7 @@ emit_output_reload_insns (struct insn_ch
 	      /* We'd have to add extra code to handle this case.  */
 	      gcc_assert (tertiary_reload < 0);
 
-	      emit_insn ((GEN_FCN (rl->secondary_out_icode)
+	      emit_insn ((GEN_FCN3 (rl->secondary_out_icode)
 			  (real_old, second_reloadreg, reloadreg)));
 	      special = 1;
 	    }
@@ -7691,7 +7691,7 @@ emit_output_reload_insns (struct insn_ch
 
 		  gen_reload (reloadreg, second_reloadreg,
 			      rl->opnum, rl->when_needed);
-		  emit_insn ((GEN_FCN (tertiary_icode)
+		  emit_insn ((GEN_FCN3 (tertiary_icode)
 			      (real_old, reloadreg, third_reloadreg)));
 		  special = 1;
 		}
