[backport gcc-4.8/trunk r189808 <mikpe@it.uu.se>]

gcc/

2012-07-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	PR target/54051
	* config/arm/arm.c (arm_print_operand_address): Remove superfluous
	printing of 0.
	* config/arm/neon.md ("neon_vld3_lane<mode>":VD): Remove alignment
	specifier.
	("neon_vld3_lane<mode>":VMQ): Likewise.
	("neon_vld3_dup<mode>":VDX): Likewise.
	("neon_vst3_lane<mode>":VD): Likewise.
	("neon_vst3_lane<mode>":VMQ): Likewise.

gcc/testsuite/

2012-07-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	PR target/54051
	* gcc.target/arm/pr54051.c: New.
	* gcc.target/arm/vfp-1.c: Adjust test.

--- gcc-4.7.3/gcc/config/arm/arm.c.~1~	2013-03-18 12:52:08.000000000 +0100
+++ gcc-4.7.3/gcc/config/arm/arm.c	2013-05-12 12:48:22.210560168 +0200
@@ -17880,7 +17880,7 @@ arm_print_operand_address (FILE *stream,
       int is_minus = GET_CODE (x) == MINUS;
 
       if (GET_CODE (x) == REG)
-	asm_fprintf (stream, "[%r, #0]", REGNO (x));
+	asm_fprintf (stream, "[%r]", REGNO (x));
       else if (GET_CODE (x) == PLUS || is_minus)
 	{
 	  rtx base = XEXP (x, 0);
--- gcc-4.7.3/gcc/config/arm/neon.md.~1~	2012-08-20 12:18:36.000000000 +0200
+++ gcc-4.7.3/gcc/config/arm/neon.md	2013-05-12 12:48:22.210560168 +0200
@@ -4733,7 +4733,7 @@ (define_insn "neon_vld3_lane<mode>"
   ops[2] = gen_rtx_REG (DImode, regno + 4);
   ops[3] = operands[1];
   ops[4] = operands[3];
-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %3",
                    ops);
   return "";
 }
@@ -4765,7 +4765,7 @@ (define_insn "neon_vld3_lane<mode>"
   ops[2] = gen_rtx_REG (DImode, regno + 8);
   ops[3] = operands[1];
   ops[4] = GEN_INT (lane);
-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %3",
                    ops);
   return "";
 }
@@ -4787,7 +4787,7 @@ (define_insn "neon_vld3_dup<mode>"
       ops[1] = gen_rtx_REG (DImode, regno + 2);
       ops[2] = gen_rtx_REG (DImode, regno + 4);
       ops[3] = operands[1];
-      output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops);
+      output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %3", ops);
       return "";
     }
   else
@@ -4905,7 +4905,7 @@ (define_insn "neon_vst3_lane<mode>"
   ops[2] = gen_rtx_REG (DImode, regno + 2);
   ops[3] = gen_rtx_REG (DImode, regno + 4);
   ops[4] = operands[2];
-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %0",
                    ops);
   return "";
 }
@@ -4937,7 +4937,7 @@ (define_insn "neon_vst3_lane<mode>"
   ops[2] = gen_rtx_REG (DImode, regno + 4);
   ops[3] = gen_rtx_REG (DImode, regno + 8);
   ops[4] = GEN_INT (lane);
-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %0",
                    ops);
   return "";
 }
--- gcc-4.7.3/gcc/testsuite/gcc.target/arm/pr54051.c.~1~	1970-01-01 01:00:00.000000000 +0100
+++ gcc-4.7.3/gcc/testsuite/gcc.target/arm/pr54051.c	2013-05-12 12:48:22.210560168 +0200
@@ -0,0 +1,20 @@
+/* { dg-do assemble }  */
+/* { dg-require-effective-target arm_neon }  */
+/* { dg-options "-O2" }  */
+/* { dg-add-options arm_neon }  */
+
+#include <arm_neon.h>
+
+int32_t a __attribute__ ((aligned (64)));
+
+int32x2x3_t test (void)
+{
+  return vld3_dup_s32 (&a);
+}
+
+int32x2x3_t test1 (void)
+{
+  int32x2x3_t res ;
+  return vld3_lane_s32 (&a, res, 1);
+}
+
--- gcc-4.7.3/gcc/testsuite/gcc.target/arm/vfp-1.c.~1~	2011-08-04 12:50:02.000000000 +0200
+++ gcc-4.7.3/gcc/testsuite/gcc.target/arm/vfp-1.c	2013-05-12 12:48:22.210560168 +0200
@@ -129,7 +129,7 @@ void test_ldst (float f[], double d[]) {
   /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */
   /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
   /* { dg-final { scan-assembler "add.+ r0, #1024" } } */
-  /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\], #0\\\]\n" } } */
+  /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\]\\\]\n" } } */
   f[256] = f[255] + f[-255];
 
   /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */
