[backport from gcc-4.7/trunk ] Date: Mon, 14 Feb 2011 14:20:43 +0000 From: Andrew Stubbs Subject: [PATCH][ARM] Tweak arm_class_likely_spilled_p, MODE_BASE_REG_CLASS for Thumb-2 List-Archive: This patch is a rework of an old one: http://gcc.gnu.org/ml/gcc-patches/2010-06/msg01080.html The ARM parts of that patch were approved, but the target independent parts were never reviewed (AFAICT), and the patch no longer applies. I've updated the target-specific parts. As far as I can tell, the target independent parts are no longer required, so I've dropped them. Tested with no regressions for ARM mode and Thumb2 mode. OK? Andrew gcc/ 2011-03-06 Andrew Stubbs Julian Brown Mark Shinwell * config/arm/arm.h (arm_class_likely_spilled_p): Check against LO_REGS only for Thumb-1. (MODE_BASE_REG_CLASS): Restrict base registers to those which can be used in short instructions when optimising for size on Thumb-2. --- gcc-4.6.1/gcc/config/arm/arm.c.~1~ 2011-05-05 10:39:40.000000000 +0200 +++ gcc-4.6.1/gcc/config/arm/arm.c 2011-09-21 17:52:10.000000000 +0200 @@ -22304,14 +22304,16 @@ arm_preferred_simd_mode (enum machine_mo /* Implement TARGET_CLASS_LIKELY_SPILLED_P. - We need to define this for LO_REGS on thumb. Otherwise we can end up - using r0-r4 for function arguments, r7 for the stack frame and don't - have enough left over to do doubleword arithmetic. */ - + We need to define this for LO_REGS on Thumb-1. Otherwise we can end up + using r0-r4 for function arguments, r7 for the stack frame and don't have + enough left over to do doubleword arithmetic. For Thumb-2 all the + potentially problematic instructions accept high registers so this is not + necessary. Care needs to be taken to avoid adding new Thumb-2 patterns + that require many low registers. */ static bool arm_class_likely_spilled_p (reg_class_t rclass) { - if ((TARGET_THUMB && rclass == LO_REGS) + if ((TARGET_THUMB1 && rclass == LO_REGS) || rclass == CC_REG) return true; --- gcc-4.6.1/gcc/config/arm/arm.h.~1~ 2011-01-29 04:20:57.000000000 +0100 +++ gcc-4.6.1/gcc/config/arm/arm.h 2011-09-21 17:52:10.000000000 +0200 @@ -1185,7 +1185,7 @@ enum reg_class when addressing quantities in QI or HI mode; if we don't know the mode, then we must be conservative. */ #define MODE_BASE_REG_CLASS(MODE) \ - (TARGET_32BIT ? CORE_REGS : \ + (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ (((MODE) == SImode) ? BASE_REGS : LO_REGS)) /* For Thumb we can not support SP+reg addressing, so we return LO_REGS