`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 04/17/2017 04:34:00 PM // Design Name: Oscar Castro // Module Name: mat_mul // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: Matrix Multiplication 32x32 [32 bits] // ////////////////////////////////////////////////////////////////////////////////// module mat_mul # ( parameter integer DIM_LOG = 0, // The API needs this one, but we don't use it. parameter DCTSIZE = 8, // Number of rows and colums (from 1) parameter DCTSIZE2 = DCTSIZE*DCTSIZE, // number of elements of the matrix 8*8 parameter DATA_WIDTH = 16, parameter RESET = 0, parameter RECEIVE = 1, parameter ORDER = 2, parameter CAL = 3, parameter SEND = 4 ) ( input wire s00_axi_aclk, // Input clock input wire s00_axi_aresetn, // reset output reg s00_axis_tready, // SEND Ready input wire [DATA_WIDTH-1 : 0] s00_axis_tdata, // RECEIVE Data Matrix A,B [31:0] input wire s00_axis_tlast, // RECEIVE Last data input wire s00_axis_tvalid, // RECEIVE Valid output reg m00_axis_tvalid, // SEND Valid output reg [DATA_WIDTH-1 : 0] m00_axis_tdata, // SEND Data Matrix R [31:0] output reg [(DATA_WIDTH/8)-1 : 0] m00_axis_tstrb, // output reg m00_axis_tlast, // SEND Last data input wire m00_axis_tready, // RECEIVE Ready input wire sel, // Select Matrix A(0) B(1) input wire start // start computation. ); reg [15 : 0] mem_A [0 : 64]; //[0 : DCTSIZE2]; // Block RAM to hold matrix A -------- [15:0] mem_A [0:16] reg [15 : 0] mem_B [0 : 64]; //[0 : DCTSIZE2]; // BRAM to hold matrix B ------------- [15:0] mem_B [0:16] reg [15 : 0] mem_S [0 : 130]; //[0 : DCTSIZE2]; // BRAM to hold the result matrix ---- [15:0] mem_C [0:16] reg [6 : 0] In[0 : 63]; //[0 : DCTSIZE2]; // BRAM to hold the result matrix ---- [15:0] mem_C [0:16] reg [15 : 0] addrIn; // address line used to fill in the matrices A and B -------------- [8:0] reg [15 : 0] addrOut; // address line used to write back the results into the memory ---- [8:0] reg [3 : 0] row; // row counter; indicates the current row of multiplication (4 bits) reg [3 : 0] col; // column counter; indicates the current column of multiplication (4 bits) // ******************************** reg [2:0] state; reg [9:0] NumCR = 0; // number to compare max an min 0 or 7 reg [15:0] count = 1; reg [15:0] memCnt = 0; //Counter of the memory reg InDec = 1'b0; // flag to increase or decrease rows and columns reg flag = 1'b0; // flag to compare when the row and columns are '0' and '7' and it decides if increment or decrement (cuando ya se repitio el numero (2 veces)) reg B1 = 1'b0; // flag to compare reg B2 = 1'b1; // flag to compare reg Z = 1'b0; initial begin m00_axis_tvalid = 1'b0; m00_axis_tdata = 0; m00_axis_tlast = 1'b0; addrIn = 0; addrOut = 0; row = 0; col = 0; In[0]= 0; In[1]= 1; In[2]= 5; In[3]= 6; In[4]= 14; In[5]= 15; In[6]= 27; In[7]= 28; In[8]= 2; In[9]= 4; In[10]=7; In[11]=13; In[12]=16; In[13]=26; In[14]=29; In[15]=42; In[16]=3; In[17]=8; In[18]=12; In[19]=17; In[20]=25; In[21]=30; In[22]=41; In[23]=43; In[24]=9; In[25]=11; In[26]=18; In[27]=24; In[28]=31; In[29]=40; In[30]=44; In[31]=53; In[32]=10; In[33]=19; In[34]=23; In[35]=32; In[36]=39; In[37]=45; In[38]=52; In[39]=54; In[40]=20; In[41]=22; In[42]=33; In[43]=38; In[44]=46; In[45]=51; In[46]=55; In[47]=60; In[48]=21; In[49]=34; In[50]=37; In[51]=47; In[52]=50; In[53]=56; In[54]=59; In[55]=61; In[56]=35; In[57]=36; In[58]=48; In[59]=49; In[60]=57; In[61]=58; In[62]=62; In[63]=63; end always @ (posedge s00_axi_aclk) begin if (!s00_axi_aresetn) begin addrIn = 0; s00_axis_tready = 1'b0; state <= RESET; end else begin case(state) RESET: begin // clean the Matix A,B m00_axis_tlast = 1'b0; m00_axis_tvalid = 1'b0; if (addrIn < DCTSIZE2) begin mem_A[addrIn] = 0; mem_B[addrIn] = 0; mem_S[addrIn] = 0; addrIn = addrIn + 1; end else begin addrIn = 0; addrOut = 0; NumCR = 0; B1 = 1'b0; B2 = 1'b1; InDec = 1'b0; row = 0; col = 0; count = 1; memCnt = 0; state <= RECEIVE; end end RECEIVE: begin // Receive data from the Master s00_axis_tready = 1'b1; if (s00_axis_tvalid) begin mem_A[In[addrIn]] = s00_axis_tdata; addrIn = addrIn + 1; end else if(start) begin s00_axis_tready = 1'b0; addrIn = 0; addrOut = 0; NumCR = 0; B1 = 1'b0; B2 = 1'b1; InDec = 1'b0; Z = 1'b0; state <= CAL; end end CAL: begin // Realize the counting in the ordered matrix if(!Z) begin if(mem_A[addrIn] == mem_A[addrIn+1]) begin count = count + 1; addrIn = addrIn + 1; if(addrIn+1 >= DCTSIZE2) begin mem_S[addrOut] = count; mem_S[addrOut+1] = mem_A[addrIn]; memCnt = memCnt + 1; Z = 1'b1; end end else begin mem_S[addrOut] = count; mem_S[addrOut+1] = mem_A[addrIn]; memCnt = memCnt + 2; addrOut = addrOut + 2; addrIn = addrIn + 1; count = 1; if(addrIn+1 >= DCTSIZE2) begin mem_S[addrOut] = count; mem_S[addrOut+1] = mem_A[addrIn]; memCnt = memCnt + 1; Z = 1'b1; end end end else begin addrIn = 0; addrOut = 0; Z = 1'b0; //$display("COUNTER: %d",memCnt); state <= SEND; end end SEND: begin // Send the Resulting Matrix if(m00_axis_tready) begin m00_axis_tstrb = 4'hf; m00_axis_tdata = mem_S[addrOut]; //$display("Mem_S(%d) : [%d]",addrOut, mem_S[addrOut]); $display("Mem_S(%d) : [%d]",addrOut, mem_S[addrOut]); m00_axis_tvalid = 1'b1; addrOut = addrOut + 1; if(addrOut > memCnt) begin m00_axis_tlast = 1'b1; state <= RESET; end end end endcase end end endmodule /* `timescale 1ns / 1ps //////////////////////////////VERSION 2 ////////////////////////////////////// // Company: // Engineer: // // Create Date: 04/17/2017 04:34:00 PM // Design Name: Oscar Castro // Module Name: mat_mul // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: Matrix Multiplication 32x32 [32 bits] // ////////////////////////////////////////////////////////////////////////////////// module mat_mul # ( parameter DCTSIZE = 8, //Number of rows and colums (from 0, it means if 3 => 4 colums and rows) parameter DCTSIZE2 = DCTSIZE*DCTSIZE, // number of elements of the matrix 8*8 parameter DATA_WIDTH = 16, parameter RESET = 0, parameter RECEIVE = 1, parameter ORDER = 2, parameter CAL = 3, parameter SEND = 4 ) ( input wire s00_axi_aclk, // Input clock input wire s00_axi_aresetn, // reset output reg s00_axis_tready, // SEND Ready input wire [DATA_WIDTH-1 : 0] s00_axis_tdata, // RECEIVE Data Matrix A,B [31:0] input wire s00_axis_tlast, // RECEIVE Last data input wire s00_axis_tvalid, // RECEIVE Valid output reg m00_axis_tvalid, // SEND Valid output reg [DATA_WIDTH-1 : 0] m00_axis_tdata, // SEND Data Matrix R [31:0] output reg [(DATA_WIDTH/8)-1 : 0] m00_axis_tstrb, // output reg m00_axis_tlast, // SEND Last data input wire m00_axis_tready, // RECEIVE Ready input wire sel, // Select Matrix A(0) B(1) input wire start // start computation. ); reg [15 : 0] mem_A [0 : 64]; //[0 : DCTSIZE2]; // Block RAM to hold matrix A -------- [15:0] mem_A [0:16] reg [15 : 0] mem_B [0 : 64]; //[0 : DCTSIZE2]; // BRAM to hold matrix B ------------- [15:0] mem_B [0:16] reg [15 : 0] mem_S [0 : 130]; //[0 : DCTSIZE2]; // BRAM to hold the result matrix ---- [15:0] mem_C [0:16] reg [6 : 0] In[0 : 63]; //[0 : DCTSIZE2]; // BRAM to hold the result matrix ---- [15:0] mem_C [0:16] reg [15 : 0] addrIn; // address line used to fill in the matrices A and B -------------- [8:0] reg [15 : 0] addrOut; // address line used to write back the results into the memory ---- [8:0] //reg [DCTSIZE : 0] addr_A; // address line used to read matrix A during multiplication (10 bits) ****************** (wire) //reg [DCTSIZE : 0] addr_B; // address line used to read matrix B during multiplication (10 bits)******************* (wire) //reg [DCTSIZE : 0] addr_R; // address line used to write to the result matrix during multiplication (10 bits)****** (wire) //reg [DCTSIZE : 0] A_cnt; // row counter; indicates the current row of multiplication //reg [DCTSIZE : 0] B_cnt; // column counter; indicates the current column of multiplication reg [3 : 0] row; // row counter; indicates the current row of multiplication (4 bits) reg [3 : 0] col; // column counter; indicates the current column of multiplication (4 bits) //reg [DATA_WIDTH-1 : 0] mac; // accumulator; accumulates the previous mad (32 Bits) // ******************************** reg [2:0] state; reg InDec = 1'b0; // flag to increase or decrease rows and columns reg flag = 1'b0; // flag to compare when the row and columns are '0' and '7' and it decides if increment or decrement (cuando ya se repitio el numero (2 veces)) reg [9:0] NumCR = 0; // number to compare max an min 0 or 7 reg B1 = 1'b0; // flag to compare reg B2 = 1'b1; // flag to compare reg [15:0] count = 1; reg [15:0] memCnt = 0; //Counter of the memory reg Z = 1'b0; initial begin m00_axis_tvalid = 1'b0; m00_axis_tdata = 0; m00_axis_tlast = 1'b0; addrIn = 0; addrOut = 0; row = 0; col = 0; In[0]= 0; In[1]= 1; In[2]= 5; In[3]= 6; In[4]= 14; In[5]= 15; In[6]= 27; In[7]= 28; In[8]= 2; In[9]= 4; In[10]=7; In[11]=13; In[12]=16; In[13]=26; In[14]=29; In[15]=42; In[16]=3; In[17]=8; In[18]=12; In[19]=17; In[20]=25; In[21]=30; In[22]=41; In[23]=43; In[24]=9; In[25]=11; In[26]=18; In[27]=24; In[28]=31; In[29]=40; In[30]=44; In[31]=53; In[32]=10; In[33]=19; In[34]=23; In[35]=32; In[36]=39; In[37]=45; In[38]=52; In[39]=54; In[40]=20; In[41]=22; In[42]=33; In[43]=38; In[44]=46; In[45]=51; In[46]=55; In[47]=60; In[48]=21; In[49]=34; In[50]=37; In[51]=47; In[52]=50; In[53]=56; In[54]=59; In[55]=61; In[56]=35; In[57]=36; In[58]=48; In[59]=49; In[60]=57; In[61]=58; In[62]=62; In[63]=63; end always @ (posedge s00_axi_aclk) begin if (!s00_axi_aresetn) begin addrIn = 0; s00_axis_tready = 1'b0; state <= RESET; end else begin case(state) RESET: begin // clean the Matix A,B m00_axis_tlast = 1'b0; m00_axis_tvalid = 1'b0; if (addrIn < DCTSIZE2) begin mem_A[addrIn] = 0; mem_B[addrIn] = 0; mem_S[addrIn] = 0; addrIn = addrIn + 1; end else begin addrIn = 0; addrOut = 0; NumCR = 0; B1 = 1'b0; B2 = 1'b1; InDec = 1'b0; row = 0; col = 0; count = 1; memCnt = 0; state <= RECEIVE; end end RECEIVE: begin // Receive data from the Master s00_axis_tready = 1'b1; if (s00_axis_tvalid) begin //mem_A[addrIn] = s00_axis_tdata; mem_A[In[addrIn]] = s00_axis_tdata; //$display("mem_A[%d] : %d", In[addrIn], mem_A[In[addrIn]]); addrIn = addrIn + 1; end else if(start) begin s00_axis_tready = 1'b0; addrIn = 0; addrOut = 0; NumCR = 0; B1 = 1'b0; B2 = 1'b1; InDec = 1'b0; Z = 1'b0; state <= CAL; //state <= ORDER; end end CAL: begin // Realize the counting in the ordered matrix if(!Z) begin if(mem_A[addrIn] == mem_A[addrIn+1]) begin count = count + 1; addrIn = addrIn + 1; if(addrIn+1 >= 64) begin mem_S[addrOut] = count; mem_S[addrOut+1] = mem_A[addrIn]; memCnt = memCnt + 1; Z = 1'b1; end end else begin mem_S[addrOut] = count; mem_S[addrOut+1] = mem_A[addrIn]; //$display("MemIn(%d) : %d MemOut(%d) : %d MemOut(%d) : %d",addrIn,mem_A[addrIn], addrOut, mem_S[addrOut],addrOut+1, mem_S[addrOut+1]); //$display("MemOut(%d) : %d\n", addrOut+1, mem_S[addrOut+1]); memCnt = memCnt + 2; addrOut = addrOut + 2; addrIn = addrIn + 1; count = 1; //$display("MemIn %d : %d", addrIn, mem_A[addrIn]); if(addrIn+1 >= 64) begin //$display("MemIn: %d MemOut: %d", addrIn, addrOut); mem_S[addrOut] = count; mem_S[addrOut+1] = mem_A[addrIn]; memCnt = memCnt + 1; //$display("MemOut(%d) : %d MemOut(%d) : %d", addrOut, mem_S[addrOut],addrOut+1, mem_S[addrOut+1]); //$display("MemCnt %d", memCnt); Z = 1'b1; end end end else begin //$display("MemIn %d MemOut: %d", addrIn, addrOut); addrIn = 0; addrOut = 0; Z = 1'b0; $display("COUNTER: %d",memCnt); state <= SEND; end end SEND: begin // Send the Resulting Matrix //$display("SEND"); if(m00_axis_tready) begin m00_axis_tstrb = 4'hf; m00_axis_tdata = mem_S[addrOut]; //$display("Mem_S(%d) : [%d]",addrOut, mem_S[addrOut]); $display("Mem_S(%d) : [%d]",addrOut, mem_S[addrOut]); m00_axis_tvalid = 1'b1; addrOut = addrOut + 1; if(addrOut > memCnt) begin m00_axis_tlast = 1'b1; state <= RESET; end end end endcase end end endmodule */ /* `timescale 1ns / 1ps ///////////////////////// VERSION 1 ////////////////////////////////////// // Company: // Engineer: // // Create Date: 04/17/2017 04:34:00 PM // Design Name: Oscar Castro // Module Name: mat_mul // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: Matrix Multiplication 32x32 [32 bits] // ////////////////////////////////////////////////////////////////////////////////// module mat_mul # ( parameter DCTSIZE = 8, //Number of rows and colums (from 0, it means if 3 => 4 colums and rows) parameter DCTSIZE2 = DCTSIZE*DCTSIZE, // number of elements of the matrix 8*8 parameter DATA_WIDTH = 16, //parameter DIM_LOG = 5, //Number of rows and colums (from 0, it means if 3 => 4 colums and rows) //parameter X = DIM_LOG, //5, // Accelerator 1 = 1X, 2 = 4X, 3 = 8X, 4 = 16X, 5 = 32X. //parameter DIM = 2**DIM_LOG, //2**DIM_log, // 2**5 = 32 [Col and Row's number] //parameter SIZE = DIM*DIM, // 32 * 32 = 1024 [number of elements of the matrix] //parameter SIZE_LOG = 2*DIM_LOG, // 2 * 5 = 10 [number in bits for the elements (10 bits = 1024)] parameter RESET = 0, parameter RECEIVE = 1, parameter ORDER = 2, parameter CAL = 3, parameter SEND = 4 ) ( input wire s00_axi_aclk, // Input clock input wire s00_axi_aresetn, // reset output reg s00_axis_tready, // SEND Ready input wire [DATA_WIDTH-1 : 0] s00_axis_tdata, // RECEIVE Data Matrix A,B [31:0] input wire s00_axis_tlast, // RECEIVE Last data input wire s00_axis_tvalid, // RECEIVE Valid output reg m00_axis_tvalid, // SEND Valid output reg [DATA_WIDTH-1 : 0] m00_axis_tdata, // SEND Data Matrix R [31:0] output reg [(DATA_WIDTH/8)-1 : 0] m00_axis_tstrb, // output reg m00_axis_tlast, // SEND Last data input wire m00_axis_tready, // RECEIVE Ready input wire sel, // Select Matrix A(0) B(1) input wire start // start computation. ); //reg [DATA_WIDTH-1 : 0] mem_A [0 : 15]; //[0 : DCTSIZE2]; // Block RAM to hold matrix A -------- [15:0] mem_A [0:16] reg [15 : 0] mem_A [0 : 64]; //[0 : DCTSIZE2]; // Block RAM to hold matrix A -------- [15:0] mem_A [0:16] reg [15 : 0] mem_B [0 : 64]; //[0 : DCTSIZE2]; // BRAM to hold matrix B ------------- [15:0] mem_B [0:16] reg [15 : 0] mem_R [0 : 64]; //[0 : DCTSIZE2]; // BRAM to hold the result matrix ---- [15:0] mem_C [0:16] reg [15 : 0] mem_S [0 : 130]; //[0 : DCTSIZE2]; // BRAM to hold the result matrix ---- [15:0] mem_C [0:16] //reg [DATA_WIDTH-1 : 0] mat_A; // item read out from matrix A ---------------- [31:0] //reg [DATA_WIDTH-1 : 0] mat_B; // item read out from matrix B ------------------ [31:0] //reg [DCTSIZE : 0] addrIn; // address line used to fill in the matrices A and B -------------- [8:0] reg [15 : 0] addrIn; // address line used to fill in the matrices A and B -------------- [8:0] reg [15 : 0] addrOut; // address line used to write back the results into the memory ---- [8:0] //reg [DCTSIZE : 0] addr_A; // address line used to read matrix A during multiplication (10 bits) ****************** (wire) //reg [DCTSIZE : 0] addr_B; // address line used to read matrix B during multiplication (10 bits)******************* (wire) //reg [DCTSIZE : 0] addr_R; // address line used to write to the result matrix during multiplication (10 bits)****** (wire) //reg [DCTSIZE : 0] A_cnt; // row counter; indicates the current row of multiplication //reg [DCTSIZE : 0] B_cnt; // column counter; indicates the current column of multiplication reg [3 : 0] row; // row counter; indicates the current row of multiplication (4 bits) reg [3 : 0] col; // column counter; indicates the current column of multiplication (4 bits) //reg [DATA_WIDTH-1 : 0] mac; // accumulator; accumulates the previous mad (32 Bits) // ******************************** reg [2:0] state; reg InDec = 1'b0; // flag to increase or decrease rows and columns reg flag = 1'b0; // flag to compare when the row and columns are '0' and '7' and it decides if increment or decrement (cuando ya se repitio el numero (2 veces)) reg [9:0] NumCR = 0; // number to compare max an min 0 or 7 reg B1 = 1'b0; // flag to compare reg B2 = 1'b1; // flag to compare reg [15:0] count = 1; reg [15:0] memCnt = 0; //Counter of the memory reg Z = 1'b0; initial begin m00_axis_tvalid = 1'b0; m00_axis_tdata = 0; m00_axis_tlast = 1'b0; addrIn = 0; addrOut = 0; //addr_A = 0; //addr_B = 0; //addr_R = 0; //A_cnt = 0; //B_cnt = 0; row = 0; col = 0; //mac = 0; end always @ (posedge s00_axi_aclk) begin if (!s00_axi_aresetn) begin addrIn = 0; s00_axis_tready = 1'b0; state <= RESET; end else begin case(state) RESET: begin // clean the Matix A,B m00_axis_tlast = 1'b0; m00_axis_tvalid = 1'b0; if (addrIn < DCTSIZE2) begin //2*DCTSIZE2 //////////////////////////////////////////// //$display("RESET 11 [%d]", addrIn); mem_A[addrIn] = 0; mem_B[addrIn] = 0; mem_S[addrIn] = 0; //16'hFFFF; //$display("mem_S[%d] %d",addrIn,mem_S[addrIn]); //mem_S[(addrIn+64)] = 0; addrIn = addrIn + 1; end else begin addrIn = 0; addrOut = 0; //addr_A = 0; //addr_R = 0; NumCR = 0; B1 = 1'b0; B2 = 1'b1; InDec = 1'b0; row = 0; col = 0; count = 1; memCnt = 0; state <= RECEIVE; end end RECEIVE: begin // Receive data from the Master s00_axis_tready = 1'b1; if (s00_axis_tvalid) begin mem_B[addrIn] = s00_axis_tdata; addrIn = addrIn + 1; end else if(start) begin s00_axis_tready = 1'b0; addrIn = 0; addrOut = 0; NumCR = 0; B1 = 1'b0; B2 = 1'b1; InDec = 1'b0; Z = 1'b0; state <= ORDER; end end ORDER: begin // Receive data from the Master if(addrIn < DCTSIZE2) begin mem_A[addrIn] = mem_B[((DCTSIZE)*row)+col]; //$display("mem_A[%d][%d] = Mem %d: %d",row,col,((DCTSIZE)*row)+col, mem_A[((DCTSIZE)*row)+col]); //if(row+col == (2*(DCTSIZE-1))) $stop; // row+columns = 14 if(row == (DCTSIZE-1) && col == 0) begin // row=7 && col=0 NumCR = DCTSIZE-1; B1 = 1'b1; B2 = 1'b0; end if((row == NumCR) && (flag == B1)) begin // row=0 && flag=0 col = col + 1; flag = ~flag; InDec = ~InDec; end else if((col == NumCR) && (flag == B2)) begin // col=0 && flag=1 row = row + 1; flag = ~flag; InDec = ~InDec; end else if(InDec) begin //InDec=1 row = row+1; col = col-1; end else begin //InDec=0 row = row-1; col = col+1; end addrIn = addrIn + 1; end else begin //if(start) begin //s00_axis_tready = 1'b0; addrIn = 0; NumCR = 0; B1 = 1'b0; B2 = 1'b1; InDec = 1'b0; Z = 1'b0; //row = 0; state <= CAL; end end CAL: begin // Realize the counting in the ordered matrix //******************* // if(addrIn == 128) // $stop; // else begin // mem_S[100] = 100; // $display("mem_S[%d] : %d",addrIn, mem_S[addrIn]); // addrIn = addrIn + 1; // end //******************* if(!Z) begin if(mem_A[addrIn] == mem_A[addrIn+1]) begin count = count + 1; addrIn = addrIn + 1; if(addrIn+1 >= 64) begin mem_S[addrOut] = count; mem_S[addrOut+1] = mem_A[addrIn]; memCnt = memCnt + 1; Z = 1'b1; end end else begin mem_S[addrOut] = count; mem_S[addrOut+1] = mem_A[addrIn]; //$display("MemIn(%d) : %d MemOut(%d) : %d MemOut(%d) : %d",addrIn,mem_A[addrIn], addrOut, mem_S[addrOut],addrOut+1, mem_S[addrOut+1]); //$display("MemOut(%d) : %d\n", addrOut+1, mem_S[addrOut+1]); memCnt = memCnt + 2; addrOut = addrOut + 2; addrIn = addrIn + 1; count = 1; //$display("MemIn %d : %d", addrIn, mem_A[addrIn]); if(addrIn+1 >= 64) begin //$display("MemIn: %d MemOut: %d", addrIn, addrOut); mem_S[addrOut] = count; mem_S[addrOut+1] = mem_A[addrIn]; memCnt = memCnt + 1; //$display("MemOut(%d) : %d MemOut(%d) : %d", addrOut, mem_S[addrOut],addrOut+1, mem_S[addrOut+1]); //$display("MemCnt %d", memCnt); Z = 1'b1; end end end else begin //$display("MemIn %d MemOut: %d", addrIn, addrOut); addrIn = 0; addrOut = 0; Z = 1'b0; $display("COUNTER: %d",memCnt); state <= SEND; end end SEND: begin // Send the Resulting Matrix //$display("SEND"); if(m00_axis_tready) begin m00_axis_tstrb = 4'hf; m00_axis_tdata = mem_S[addrOut]; $display("Mem_S(%d) : [%d]",addrOut, mem_S[addrOut]); m00_axis_tvalid = 1'b1; addrOut = addrOut + 1; if(addrOut > memCnt) begin m00_axis_tlast = 1'b1; state <= RESET; end end end endcase end end endmodule */