We study channel systems whose behaviour (sending and receiving messages
via unbounded FIFO channels) must follow given timing constraints
specifying the execution speeds of the local components. We propose
Communicating Timed Automata (CTA) to model such systems. The goal is to
study the borderline between decidable and undecidable classes of channel
systems in the timed setting. Our technical results include: (1) CTA with
one channel without shared states in the form $(A_1,A_2, c_{1,2})$ is
equivalent to one-counter machine, implying that verification problems
such as checking state reachability and channel boundedness are decidable,
and (2) CTA with two channels without sharing states in the form
$(A_1,A_2,A_3, c_{1,2},c_{2,3})$ has the power of Turing machines. Note
that in the untimed setting, these systems are no more expressive than
finite state machines. This shows that the capability of synchronizing on
time makes it substantially more difficult to verify channel systems.