[initial patch to add sync builtins for m68k in gcc-4.6,
 everything except sync.md is backported from gcc-4.7, but
 sync.md cannot be based on the one in gcc-4.7 so instead
 it loosely follows the i386 and sparc sync.md files]

gcc/

2012-03-10  Mikael Pettersson  <mikpe@it.uu.se>

	* config/m68k/m68k.md (UNSPECV_CAS): New.
	* config/m68k/sync.md: New file.

	Backport from mainline:
	2011-11-26  Richard Hendersson  <rth@redhat.com>

	* config/m68k/m68k.md (I): New mode iterator.
	(sz): New mode attribute.

	Backport from mainline:
	2011-12-19  Andreas Schwab  <schwab@linux-m68k.org>

	PR target/51532
	* config/m68k/m68k.h (FL_CAS, TARGET_CAS): Define.
	* config/m68k/m68k.c (FL_FOR_isa_20): Add FL_CAS.
	* config/m68k/sync.md: Use TARGET_CAS instead of (TARGET_68020 ||
	TARGET_68040).

--- gcc-4.6.3/gcc/config/m68k/m68k.c.~1~	2011-07-31 17:09:25.000000000 +0200
+++ gcc-4.6.3/gcc/config/m68k/m68k.c	2012-03-10 21:12:27.000000000 +0100
@@ -318,7 +318,7 @@ struct gcc_target targetm = TARGET_INITI
    generated 68881 code for 68020 and 68030 targets unless explicitly told
    not to.  */
 #define FL_FOR_isa_20    (FL_FOR_isa_10 | FL_ISA_68020 \
-			  | FL_BITFIELD | FL_68881)
+			  | FL_BITFIELD | FL_68881 | FL_CAS)
 #define FL_FOR_isa_40    (FL_FOR_isa_20 | FL_ISA_68040)
 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
 
--- gcc-4.6.3/gcc/config/m68k/m68k.h.~1~	2010-11-22 02:57:50.000000000 +0100
+++ gcc-4.6.3/gcc/config/m68k/m68k.h	2012-03-10 19:49:00.000000000 +0100
@@ -232,6 +232,7 @@ along with GCC; see the file COPYING3.  
 #define FL_ISA_B     (1 << 15)
 #define FL_ISA_C     (1 << 16)
 #define FL_FIDOA     (1 << 17)
+#define FL_CAS       (1 << 18)   /* Support cas insn.  */
 #define FL_MMU 	     0   /* Used by multilib machinery.  */
 #define FL_UCLINUX   0   /* Used by multilib machinery.  */
 
@@ -242,6 +243,7 @@ along with GCC; see the file COPYING3.  
 #define TARGET_COLDFIRE_FPU	(m68k_fpu == FPUTYPE_COLDFIRE)
 #define TARGET_68881		(m68k_fpu == FPUTYPE_68881)
 #define TARGET_FIDOA		((m68k_cpu_flags & FL_FIDOA) != 0)
+#define TARGET_CAS		((m68k_cpu_flags & FL_CAS) != 0)
 
 /* Size (in bytes) of FPU registers.  */
 #define TARGET_FP_REG_SIZE	(TARGET_COLDFIRE ? 8 : 12)
--- gcc-4.6.3/gcc/config/m68k/m68k.md.~1~	2009-12-31 00:03:46.000000000 +0100
+++ gcc-4.6.3/gcc/config/m68k/m68k.md	2012-03-10 19:24:43.000000000 +0100
@@ -124,6 +124,7 @@ (define_constants
 
 (define_constants
   [(UNSPECV_BLOCKAGE	0)
+   (UNSPECV_CAS		1)
   ])
 
 ;; Registers by name.
@@ -255,6 +256,10 @@ (define_attr "enabled" ""
 	 (const_int 0)]
  	(const_int 1)))
 
+;; Mode macros for integer operations.
+(define_mode_iterator I [QI HI SI])
+(define_mode_attr sz [(QI "%.b") (HI "%.w") (SI "%.l")])
+
 ;; Mode macros for floating point operations.
 ;; Valid floating point modes
 (define_mode_iterator FP [SF DF (XF "TARGET_68881")])
@@ -7806,3 +7811,4 @@ (define_insn "ib"
   [(set_attr "type" "ib")])
 
 (include "cf.md")
+(include "sync.md")
--- gcc-4.6.3/gcc/config/m68k/sync.md.~1~	1970-01-01 01:00:00.000000000 +0100
+++ gcc-4.6.3/gcc/config/m68k/sync.md	2012-03-10 22:04:41.000000000 +0100
@@ -0,0 +1,43 @@
+;; GCC machine description for m68k synchronization instructions.
+;; Copyright (C) 2012
+;; Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_expand "sync_compare_and_swap<mode>"
+  [(parallel
+     [(set (match_operand:I 0 "register_operand" "")
+	   (match_operand:I 1 "memory_operand" ""))
+      (set (match_dup 1)
+	   (unspec_volatile:I
+	     [(match_dup 1)
+	      (match_operand:I 2 "register_operand" "")
+	      (match_operand:I 3 "register_operand" "")]
+	     UNSPECV_CAS))])]
+  "TARGET_CAS")
+
+(define_insn "*sync_compare_and_swap<mode>"
+  [(set (match_operand:I 0 "register_operand" "=d")
+	(match_operand:I 1 "memory_operand" "+m"))
+   (set (match_dup 1)
+	(unspec_volatile:I
+	  [(match_dup 1)
+	   (match_operand:I 2 "register_operand" "d")
+	   (match_operand:I 3 "register_operand" "0")]
+	  UNSPECV_CAS))]
+  "TARGET_CAS"
+  "cas<sz> %2,%0,%1")