[backport from gcc-4.7.2 r190527 ] Date: Tue, 14 Aug 2012 16:01:44 +0100 Subject: [Patch ARM] Fix PR54212 - Remove predicable attribute from Advanced SIMD patterns in the ARM backend. From: Ramana Radhakrishnan List-Archive: Hi, This fixes PR target/54212.. The problem here was we were marking a number of patterns in neon.md as predicable. Advanced SIMD instructions are not predicable in ARM state, however are allowed to exist in Thumb2 in IT blocks ( though this is a feature that is deprecated and is documented in the latest ARM ARM Issue C.B ) . This therefore removes the predicable attribute from all such instructions in the Neon backend. This is currently undergoing regression testing on armv7-a cross, will apply if no regressions and I intend backporting this atleast to 4.7 branch as this is an issue in the backend since the original days of Advanced SIMD support and the bug report was reported on the 4.7 branch where it is reproducible. I would like to take this back to 4.6 branch as well but would like to do so after it has lived for a while on trunk / 4.7 . regards, Ramana gcc/ 2012-08-20 Ramana Radhakrishnan Backport from mainline. 2012-08-15 Ramana Radhakrishnan PR target/54212 * config/arm/neon.md (vec_set_internal VD,VQ): Do not mark as predicable. Adjust asm template. (vec_setv2di_internal): Likewise. (vec_extract VD, VQ): Likewise. (vec_extractv2di): Likewise. (neon_vget_lane_sext_internal VD, VQ): Likewise. (neon_vset_lane_sext_internal VD, VQ): Likewise. (neon_vdup_n VX, V32): Likewise. (neon_vdup_nv2di): Likewise. --- gcc-4.6.3/gcc/config/arm/neon.md.~1~ 2011-06-20 13:14:50.000000000 +0200 +++ gcc-4.6.3/gcc/config/arm/neon.md 2012-09-09 16:05:05.000000000 +0200 @@ -430,10 +430,9 @@ (define_insn "vec_set_internal" elt = GET_MODE_NUNITS (mode) - 1 - elt; operands[2] = GEN_INT (elt); - return "vmov%?.\t%P0[%c2], %1"; + return "vmov.\t%P0[%c2], %1"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_mcr")]) + [(set_attr "neon_type" "neon_mcr")]) (define_insn "vec_set_internal" [(set (match_operand:VQ 0 "s_register_operand" "=w") @@ -456,10 +455,9 @@ (define_insn "vec_set_internal" operands[0] = gen_rtx_REG (mode, regno + hi); operands[2] = GEN_INT (elt); - return "vmov%?.\t%P0[%c2], %1"; + return "vmov.\t%P0[%c2], %1"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_mcr")] + [(set_attr "neon_type" "neon_mcr")] ) (define_insn "vec_setv2di_internal" @@ -476,10 +474,9 @@ (define_insn "vec_setv2di_internal" operands[0] = gen_rtx_REG (DImode, regno); - return "vmov%?\t%P0, %Q1, %R1"; + return "vmov\t%P0, %Q1, %R1"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_mcr_2_mcrr")] + [(set_attr "neon_type" "neon_mcr_2_mcrr")] ) (define_expand "vec_set" @@ -507,10 +504,9 @@ (define_insn "vec_extract" elt = GET_MODE_NUNITS (mode) - 1 - elt; operands[2] = GEN_INT (elt); } - return "vmov%?.\t%0, %P1[%c2]"; + return "vmov.\t%0, %P1[%c2]"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "vec_extract" @@ -531,10 +527,9 @@ (define_insn "vec_extract" operands[1] = gen_rtx_REG (mode, regno + hi); operands[2] = GEN_INT (elt); - return "vmov%?.\t%0, %P1[%c2]"; + return "vmov.\t%0, %P1[%c2]"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "vec_extractv2di" @@ -548,10 +543,9 @@ (define_insn "vec_extractv2di" operands[1] = gen_rtx_REG (DImode, regno); - return "vmov%?\t%Q0, %R0, %P1 @ v2di"; + return "vmov\t%Q0, %R0, %P1 @ v2di"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_int_1")] + [(set_attr "neon_type" "neon_int_1")] ) (define_expand "vec_init" @@ -2518,10 +2512,9 @@ (define_insn "neon_vget_lane_sext_ elt = GET_MODE_NUNITS (mode) - 1 - elt; operands[2] = GEN_INT (elt); } - return "vmov%?.s\t%0, %P1[%c2]"; + return "vmov.s\t%0, %P1[%c2]"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "neon_vget_lane_zext_internal" @@ -2538,10 +2531,9 @@ (define_insn "neon_vget_lane_zext_ elt = GET_MODE_NUNITS (mode) - 1 - elt; operands[2] = GEN_INT (elt); } - return "vmov%?.u\t%0, %P1[%c2]"; + return "vmov.u\t%0, %P1[%c2]"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "neon_vget_lane_sext_internal" @@ -2564,12 +2556,11 @@ (define_insn "neon_vget_lane_sext_ ops[0] = operands[0]; ops[1] = gen_rtx_REG (mode, regno + 2 * (elt / halfelts)); ops[2] = GEN_INT (elt_adj); - output_asm_insn ("vmov%?.s\t%0, %P1[%c2]", ops); + output_asm_insn ("vmov.s\t%0, %P1[%c2]", ops); return ""; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "neon_vget_lane_zext_internal" @@ -2592,12 +2583,11 @@ (define_insn "neon_vget_lane_zext_ ops[0] = operands[0]; ops[1] = gen_rtx_REG (mode, regno + 2 * (elt / halfelts)); ops[2] = GEN_INT (elt_adj); - output_asm_insn ("vmov%?.u\t%0, %P1[%c2]", ops); + output_asm_insn ("vmov.u\t%0, %P1[%c2]", ops); return ""; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_expand "neon_vget_lane" @@ -2718,10 +2708,9 @@ (define_insn "neon_vdup_n" [(set (match_operand:VX 0 "s_register_operand" "=w") (vec_duplicate:VX (match_operand: 1 "s_register_operand" "r")))] "TARGET_NEON" - "vdup%?.\t%0, %1" + "vdup.\t%0, %1" ;; Assume this schedules like vmov. - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "neon_vdup_n" @@ -2729,11 +2718,10 @@ (define_insn "neon_vdup_n" (vec_duplicate:V32 (match_operand: 1 "s_register_operand" "r,t")))] "TARGET_NEON" "@ - vdup%?.\t%0, %1 - vdup%?.\t%0, %y1" + vdup.\t%0, %1 + vdup.\t%0, %y1" ;; Assume this schedules like vmov. - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_expand "neon_vdup_ndi" @@ -2751,10 +2739,9 @@ (define_insn "neon_vdup_nv2di" (vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))] "TARGET_NEON" "@ - vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1 - vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1" - [(set_attr "predicable" "yes") - (set_attr "length" "8") + vmov\t%e0, %Q1, %R1\;vmov\t%f0, %Q1, %R1 + vmov\t%e0, %P1\;vmov\t%f0, %P1" + [(set_attr "length" "8") (set_attr "neon_type" "neon_bp_simple")] )