[backport gcc-4.7/trunk r175588 <mikpe@it.uu.se>]

From: Ramana Radhakrishnan <ramana dot radhakrishnan at linaro dot org>
Subject: [PATCH] [ARM] Fix constraint modifiers for VFP patterns.
Date: Tue, 28 Jun 2011 15:20:53 +0100
List-Archive: <http://gcc.gnu.org/ml/gcc-patches/>

Hi,

Sometime back Chung-Lin noticed that a few of the VFP patterns as below
had the '+' constraint modifiers rather than the '=' constraint
modifiers.

I've now corrected this as follows and tested this on trunk with arm-linux-gnueabi
and qemu for a v7-a neon test run. Committed.

gcc/

2011-06-28  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	* config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier
	with '=' constraint modifier.
	(*divdf3_vfp): Likewise.
	("*mulsf3_vfp"): Likewise.
	("*muldf3_vfp"): Likewise.
	("*mulsf3negsf_vfp"): Likewise.
	("*muldf3negdf_vfp"): Likewise.

--- gcc-4.6.2/gcc/config/arm/vfp.md.~1~	2011-01-20 23:03:29.000000000 +0100
+++ gcc-4.6.2/gcc/config/arm/vfp.md	2011-12-27 11:54:00.000000000 +0100
@@ -712,7 +712,7 @@ (define_insn "*subdf3_vfp"
 ;; Division insns
 
 (define_insn "*divsf3_vfp"
-  [(set (match_operand:SF	  0 "s_register_operand" "+t")
+  [(set (match_operand:SF	  0 "s_register_operand" "=t")
 	(div:SF (match_operand:SF 1 "s_register_operand" "t")
 		(match_operand:SF 2 "s_register_operand" "t")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@@ -722,7 +722,7 @@ (define_insn "*divsf3_vfp"
 )
 
 (define_insn "*divdf3_vfp"
-  [(set (match_operand:DF	  0 "s_register_operand" "+w")
+  [(set (match_operand:DF	  0 "s_register_operand" "=w")
 	(div:DF (match_operand:DF 1 "s_register_operand" "w")
 		(match_operand:DF 2 "s_register_operand" "w")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
@@ -735,7 +735,7 @@ (define_insn "*divdf3_vfp"
 ;; Multiplication insns
 
 (define_insn "*mulsf3_vfp"
-  [(set (match_operand:SF	   0 "s_register_operand" "+t")
+  [(set (match_operand:SF	   0 "s_register_operand" "=t")
 	(mult:SF (match_operand:SF 1 "s_register_operand" "t")
 		 (match_operand:SF 2 "s_register_operand" "t")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@@ -745,7 +745,7 @@ (define_insn "*mulsf3_vfp"
 )
 
 (define_insn "*muldf3_vfp"
-  [(set (match_operand:DF	   0 "s_register_operand" "+w")
+  [(set (match_operand:DF	   0 "s_register_operand" "=w")
 	(mult:DF (match_operand:DF 1 "s_register_operand" "w")
 		 (match_operand:DF 2 "s_register_operand" "w")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
@@ -754,9 +754,8 @@ (define_insn "*muldf3_vfp"
    (set_attr "type" "fmuld")]
 )
 
-
 (define_insn "*mulsf3negsf_vfp"
-  [(set (match_operand:SF		   0 "s_register_operand" "+t")
+  [(set (match_operand:SF		   0 "s_register_operand" "=t")
 	(mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
 		 (match_operand:SF	   2 "s_register_operand" "t")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@@ -766,7 +765,7 @@ (define_insn "*mulsf3negsf_vfp"
 )
 
 (define_insn "*muldf3negdf_vfp"
-  [(set (match_operand:DF		   0 "s_register_operand" "+w")
+  [(set (match_operand:DF		   0 "s_register_operand" "=w")
 	(mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
 		 (match_operand:DF	   2 "s_register_operand" "w")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"