[backport from gcc-4.7/trunk, fixes parts of PR48328 <mikpe@it.uu.se>]

Date: Fri, 12 Aug 2011 14:59:38 +0100
Subject: [Patch ARM] Fix PR target/48328 part 1
From: Ramana Radhakrishnan <ramana dot radhakrishnan at linaro dot org>
List-Archive: <http://gcc.gnu.org/ml/gcc-patches/>

Hi,

The Thumb2 tbh instruction can take half word values that are
multiplied by 2 which implies the maximum offset is 0x1FFFF when you
add it to the pc ,
rather than 0xFFF which is what the current range check of 0x2000 for
HImode values indicates. Checked that a pre-compiled insn-recog.i that
I had lying around got about 5 more tbh's *and* assembled and
generally looks sane.

Tests running for T2 v7-a on qemu. Will commit after results come out.

cheers
Ramana

gcc/

2011-08-12  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

        PR target/48328
	* config/arm/arm.h (CASE_VECTOR_SHORTEN_MODE): Fix distance
	for tbh instructions.

--- gcc-4.6.1/gcc/config/arm/arm.h.~1~	2011-01-29 04:20:57.000000000 +0100
+++ gcc-4.6.1/gcc/config/arm/arm.h	2011-09-21 17:20:44.000000000 +0200
@@ -1970,7 +1970,7 @@ typedef struct
       : min >= -4096 && max < 4096					\
       ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode)	\
       : SImode)								\
-   : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode		\
+   : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode		\
       : (max >= 0x200) ? HImode						\
       : QImode))