Mahdad Davari

mahdad.davari@it.uu.se

I have designed a full-custom low-power SAR-ADC chip in the context of a CDIO project at Linköping University. I went through the complete design flow from idea to tape-out. The chip was fabricated at AMS foundry, Austria, using 0.35 um CMOS technology with 4 metal layers, die size 520x520 um (0.2 mm2 ). Measurements on the fabricated chip revealed power consumption of 67 uW @ 100 KHz and ENOB of 7.09 bits (8-bit resolution) @ Vref=2.2V.

Besides full-custom design, I have also designed and implemented the following hardware using FPGAs:

• Digital equalizer in VHDL on Altera Cyclon II 2C70, Linköping University
• JPEG Compressor in Verilog on Xilinx Virtex II, Linköping University
• FPGA Optimized Processor (in the context of Master Thesis), available at amazon

Patents

System and method for data classification and efficient virtual cache coherence without reverse translation.
(WO2013186694A2 - June 10, 2013)

Awards

HiPEAC Paper Award - International Symposium on High Performance Computer Architecture (HPCA) 2015

Teachings