The shrinking of the geometry in the CMOS process keeps making the transistor faster for each generation, while the communication delay keeps increasing. This has forces CPU architects to think along new lines in order to create communication locality:

Clustering is a new way of lumping resources around functional units

Chip MultiProcessors (CMP) puts several CPUs, each with their local cache, on a chip

Simultaneous Multi-Threading (SMT) allows a single CPU core to schedule instructions from several parallel threads.

While clustering will have a relatively small impact on the look-and-feel of a CPU, both SMT and CMP will make thread-level parallelism visible at the CPU-level. This will force a new programming paradigms for some applications, while automatic parallelization may be the answer for others.

Executing code from several thread simultaneously may also be attractive for some real-time applications. It may simplify the task of reserving hardware resources for some time-critical services. While CMP may appear to be the obvious choice, SMT could also provide some interesting properties given the right hardware scheduling between threads.

Apart from improving the performance my introducing thread-level parallelism, CMP technology can also be used to decrease the power consumption. Running two threads at half the clock frequency may actually decrease the energy needed to perform a specific task.

This course will explore and understand the technology properties of today and tomorrow and map its impact on the different application areas.

Topics of interest The course will be centered around the questions

• What is happening with CMOS technology?
• What is happening with memory technology?
• Which of the three schemes Clustering/SMT/CMP will prevail?
• Any possible fourth scheel or hybrid solutions out there?
• Is there some clear trends?
• What are the pros and cons of each scheme given different requirements?
• What will be the effect on applications and tools?
• How can we find the desired parallelism?
• How do we best schedule threads to achieve some desired property?
• How do we decrease power consumption?

Format Six seminar lectures during four full days

• April 19: Chalmers: CMOS technology impact and modern memory technology
• May 6: Uppsala: SMT CMP
• May 26: KTH: Clustered architectures and hybrids

Examination: The course will earn you 3p. In order to get full credits for the course, we expect you to:

• Be host for at least one lecture and select and present its papers
• Complete all TP questionnaires before each presentation
• Take an active role in all the discussion

Examinators: The course is given jointly by professors:

• Mats Brorsson -- KTH
• Erik Hagersten -- Uppsla University
• Per Stenstrom -- Chalmers University

When? Spring of 2004 (April - June)

• The course starts april 19th at Chalmers. The four days of lectures will be scheduled in April - June. The preliminary dates appear above. Please sign up using the sign-up form in the menu to the left before April 15th