First	Second	Email	Phone	School	Reserach
Martin	Karlsson	martink KANELBULLE it.uu.se	018-4710000	Uppsala University
Dan	Wallin	danw KANELBULLE it.uu.se	018-4710000	Uppsala University	Optimization of memory/cache systems in shared-memory multiprocessors.
Johann	Deneux	Johann.Deneux KANELBULLE it.uu.se	018-4710000	Uppsala University	Formal methods and automated verification applied to the design of fault-tolerant systems.
Zoran	Radovic	zoranr KANELBULLE it.uu.se	018-4710000	Uppsala Universitet	My research interests are in the area of computer architecture, primarily the design of future high-performance clusters of multiprocessors. I am also interested in the compiler and code instrumentation technology, operating and run-time systems, and opportunities for software-hardware cooperation.
Håkan	Zeffer	zeffer KANELBULLE it.uu.se	018-4710000	uppsala university	HW and SW DSM systems. coherence and memory consistency issues.
Charlotta	Bååth	char KANELBULLE ce.chalmers.se	031-772 1711	Chalmers	prefetching, caching & working sets
Erik	Berg	erikberg KANELBULLE docs.uu.se	018-4710000	Uppsala	Simulation and modelling of memory system. Statistical modelling and sampling techniques. Profiling tools and optimization.
Lars	Albertsson	lalle KANELBULLE sics.se	08-6331551	Uppsala universitet	Developing simulation-based tools for debugging, profiling, and testing timing-sensitive software.
Martin	Thuresson	martin KANELBULLE ce.chalmers.se	031-7721678	Chalmers University of Technology	Design of an architecture that combines the efficiency of decidecated hardware with the programmability of a GPP on a SoC. Also looking at instruction compression and instruction translations.
Henrik	Johansson	henrikj KANELBULLE it.uu.se	018-4716253	Uppsala Universitet	Load balancing for PDE solvers using adaptive structured mesh refinement. Aims to create a general framework that automaticaly selects the optimal load balancing method with the regard to the current state of both the application and the compuer system.
Mikael	Collin	mikaelc KANELBULLE imit.kth.se	087904171	KTH	"Energy aware instruction fetch" Instruction fetch bandwith has become a bottleneck, one way to improve on the fetch bandwith is to have an ISA with a higher information density than what is the normal case for risc architectures. Through profiling the most executed instructions are selected to be encode using less bitts that normaly used for instructions. Alowing a risc processor to fetch and decode instructions of variable length will improve the fetch bandwidth and reduce the number of instruction cache accesses and BTB accesses. All resulting in energy savings in the fetch path of the processor.
Fredrik	Warg	warg KANELBULLE ce.chalmers.se	031-7721668	Chalmers	Methods for improving thread-level speculation for chip multiprocessors / multithreaded processors.
Guillaume	Girard	guillaume.girard KANELBULLE virtutech.se	0704610191	None	Development engineer at Virtutech.
Ali	Iranpour	ali.iranpour KANELBULLE cs.lth.se	0705596659	Lund University	SIMD architectures on mobile platforms for MPEG4.
Zhonghai	Lu	zhonghai KANELBULLE imit.kth.se	087904111	KTH	Design methodology for networks on chips with focus on communication refinement.
Magnus	Ekman	mekman KANELBULLE ce.chalmers.se	031-772 5229	Chalmers	How to manage main memory in future systems, especially splitting up the flat memory system into multiple levels, e.g. by compressing parts of the memory. Simulation methodologies, among other things statistical techniques. Have previously been looking at low-power and energy aware systems.
Simon	Kågström	ska KANELBULLE bth.se	0457-385875	Blekinge Institute of Technology	My research area centers around low-level performance issuses in multiprocessor and distributed systems. Until now, we have done some work on methods for porting operating systems to SMPs and are currently working on a low-overhead program instrumentation tool.
Henrik	Löf	henrik.lof KANELBULLE it.uu.se	+46184711040	Uppsala	Numerical algorithms and architecture. SW-DSM.
Tomas	Holmberg	th KANELBULLE virtutech.se	08-6900734	None	Low level simulation, systemC, interaction of simulators simulating at differnt abstraction level, and ISS.