P0: Agarwal Vikas Agarwal, M.S. Hrishikesh, Stephen W. Keckler and Doug Burger: Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures (ISCA 2000)

• The paper describes the emerging limitations of communication delay in CMOS technology and predicts that thread-level parallelism will be needed in order to stay on the CPU performance curve

P1: Beckmann Bradford M. Beckman and David A. Wood: TLC -- Transmission Line Caches (Micro 2003)

• Global interconnect can be made faster if designed with care -- but it is going to cost area and power

P2: Mudge Trevor Mudge: Power -- A First-Class Architectural Design Constraint (IEEE Computer April 2001)

• The power dissipation (and power consumption) is becoming an increasingly important design consideration for CPU designs