UU | IT | DoCS | eh TIC -- Lecture5: Assynchronous and Power 1. Who are you? Sel Ali Charlotta Dan ErikB ErikH Fredrik Guillaume HåkanS HåkanZ HenrikJ HenrikL Johann Lars Magnus MartinK MartinT Mats Mikael Per Simon Tomas Zhonghai Zoran 2. Which of the following statements are true for paper P1(Werner) and P2(Martin) 1 A simple function in the datapath would have a forward latency of at least 11 transitions in the CAM 2 A perfect MiniMIPS in 0.6um technology is slower than an Alpha 21064 at the same power consumption level 3 MiniMIPS can execute instructions concurrently 4 Caltech Asynchronous Microprocessor (CAM) had two buses 5 QDI circuit are the most robust design when it comes to variations in physical design parameters 6 MiniMIPS is twice as fast as the synchronous MIPS 7 Lutonium 051 has a single global bus 8 To obtain high data throughput MiniMIPS uses control-data decompression 3. Which of the following statements are true for paper P3 (Bose) 1 Assume a 4 stage pipeline with average utilization due to valid data of 0.5. The worst case power spike could be 75% of the maximum power. 2 Increasing the gating window always decreases the power consumption. 4 . Rate paper P2 1 Was it easy to read the paper? Sel no -- not at all no -- only marginally so neutral yes -- to some extent yes -- very much 2 Is the paper technically sound (for the time it was written)? Sel no -- not at all no -- only marginally so neutral yes -- to some extent yes -- very much 3 How do you rate the overall presentation? Sel bad not good average pretty good very good 4 Any short suggestions for improvements? 5 . Submit at least two issues to discuss at the meeting 1 Issue 1 2 Issue 2 3 Issue 3 4 Issue 4 Please, print a copy of your form and bring it to the next meeting <eh@it.uu.se>
Sel Ali Charlotta Dan ErikB ErikH Fredrik Guillaume HåkanS HåkanZ HenrikJ HenrikL Johann Lars Magnus MartinK MartinT Mats Mikael Per Simon Tomas Zhonghai Zoran
1 A simple function in the datapath would have a forward latency of at least 11 transitions in the CAM 2 A perfect MiniMIPS in 0.6um technology is slower than an Alpha 21064 at the same power consumption level 3 MiniMIPS can execute instructions concurrently 4 Caltech Asynchronous Microprocessor (CAM) had two buses 5 QDI circuit are the most robust design when it comes to variations in physical design parameters 6 MiniMIPS is twice as fast as the synchronous MIPS 7 Lutonium 051 has a single global bus 8 To obtain high data throughput MiniMIPS uses control-data decompression
1 Assume a 4 stage pipeline with average utilization due to valid data of 0.5. The worst case power spike could be 75% of the maximum power. 2 Increasing the gating window always decreases the power consumption.
1 Was it easy to read the paper? Sel no -- not at all no -- only marginally so neutral yes -- to some extent yes -- very much 2 Is the paper technically sound (for the time it was written)? Sel no -- not at all no -- only marginally so neutral yes -- to some extent yes -- very much 3 How do you rate the overall presentation? Sel bad not good average pretty good very good 4 Any short suggestions for improvements?
1 Issue 1 2 Issue 2 3 Issue 3 4 Issue 4
Please, print a copy of your form and bring it to the next meeting