UU | IT | DoCS | eh TIC -- Lecture2:Memory Technology 1. Who are you? Sel Ali Charlotta Dan ErikB ErikH Fredrik Guillaume HåkanS HåkanZ HenrikJ HenrikL Johann Lars Magnus MartinK MartinT Mats Mikael Per Simon Tomas Zhonghai Zoran 2. Check the TRUE statements for the P0 paper 1 Page mode means that data is held in the sense amps allowing multiple columns to be read in rapid succession 2 Extended Data Out DRAM does not support page mode 3 Both Synchronous Link DRAM and Rambus DRAMs use a split request/response protocol 4 Rambus DRAM is an open standard 5 Direct Rambus DRAMs are divided into 16 banks each with its own row buffer 6 Contemporary DRAM architectures are all striving to decrease the memory latency 7 Since bus transmission time accounts for up to 50% of the total latency for the simulated configurations bus speed is predicted to become a critical issue 8 Moving to wider buses will make the row access component of the memory access time more significant 3. Which (if any) of the following statements are true for paper P1 1 DRAM density of 512Mb means that there is 512Mb of memory per square centimeter of chip area 2 DRAM density is expected to increase by a factor of four during the years 2005-2010 3 It is too complex to make a memory where each cell stores more than one bit to even consider such a construction 4 The density of NAND based flash memory is increasing more than the density of DRAM 5 DRAM is roughly two magnitudes slower than the CPU today 4. In the paper P2 a RAM array is divided into macros which are divided into blocks. Which (if any) of the following statements are true? 1 Each macro needs separate decoders 2 Blocks share sense amplifiers 3 When a RAM array is divided into macros and blocks the access time decreases only until a certain point after which further sub-dividing will increase access time 4 Delay is sometimes measured in Tfo4 (where T is the Greek letter Tau) and fo4 means faculty of four 5 Access time decreases with decreased wire width 6 Redundant rows in the array are inserted in order to decrease the access time 5. Check the TRUE statements for the EXTRA paper 1 MRAM cells can be manufactured with higher density than DRAM cells 2 MRAMS do not consume any static power 3 A drawback with mixing logic and MRAM on the same die is that the fabrication technology cannot be fine-tuned for either logic or RAM -- it is a trade-off 4 Information is stored in an MRAM cell by changing polarization of a magnetic layer 5 The expected size of on-die MRAM is in the hundreds of megabytes range 6 There is a power/performance trade-off in the architecture evaluated in the paper due to the fact that MRAM writes consume more power than reads 7 Multilayer MRAM implementation increases capacity without increasing overhead in the logic layer but may be difficult to manufacture 6 . Questions about the EXTRA paper 1 What are the main advantages of MRAM? 2 What is chipstacking? 7 . Rate paper P0 1 Was it easy to read the paper? Sel no -- not at all no -- only marginally so neutral yes -- to some extent yes -- very much 2 Is the paper technically sound (for the time it was written)? Sel no -- not at all no -- only marginally so neutral yes -- to some extent yes -- very much 3 How do you rate the overall presentation? Sel bad not good average pretty good very good 4 Any short suggestions for improvements? 8 . Submit at least two issues to discuss at the meeting 1 Issue 1 2 Issue 2 3 Issue 3 4 Issue 4 Please, print a copy of your form and bring it to the next meeting <eh@it.uu.se>
Sel Ali Charlotta Dan ErikB ErikH Fredrik Guillaume HåkanS HåkanZ HenrikJ HenrikL Johann Lars Magnus MartinK MartinT Mats Mikael Per Simon Tomas Zhonghai Zoran
1 Page mode means that data is held in the sense amps allowing multiple columns to be read in rapid succession 2 Extended Data Out DRAM does not support page mode 3 Both Synchronous Link DRAM and Rambus DRAMs use a split request/response protocol 4 Rambus DRAM is an open standard 5 Direct Rambus DRAMs are divided into 16 banks each with its own row buffer 6 Contemporary DRAM architectures are all striving to decrease the memory latency 7 Since bus transmission time accounts for up to 50% of the total latency for the simulated configurations bus speed is predicted to become a critical issue 8 Moving to wider buses will make the row access component of the memory access time more significant
1 DRAM density of 512Mb means that there is 512Mb of memory per square centimeter of chip area 2 DRAM density is expected to increase by a factor of four during the years 2005-2010 3 It is too complex to make a memory where each cell stores more than one bit to even consider such a construction 4 The density of NAND based flash memory is increasing more than the density of DRAM 5 DRAM is roughly two magnitudes slower than the CPU today
1 Each macro needs separate decoders 2 Blocks share sense amplifiers 3 When a RAM array is divided into macros and blocks the access time decreases only until a certain point after which further sub-dividing will increase access time 4 Delay is sometimes measured in Tfo4 (where T is the Greek letter Tau) and fo4 means faculty of four 5 Access time decreases with decreased wire width 6 Redundant rows in the array are inserted in order to decrease the access time
1 MRAM cells can be manufactured with higher density than DRAM cells 2 MRAMS do not consume any static power 3 A drawback with mixing logic and MRAM on the same die is that the fabrication technology cannot be fine-tuned for either logic or RAM -- it is a trade-off 4 Information is stored in an MRAM cell by changing polarization of a magnetic layer 5 The expected size of on-die MRAM is in the hundreds of megabytes range 6 There is a power/performance trade-off in the architecture evaluated in the paper due to the fact that MRAM writes consume more power than reads 7 Multilayer MRAM implementation increases capacity without increasing overhead in the logic layer but may be difficult to manufacture
1 What are the main advantages of MRAM? 2 What is chipstacking?
1 Was it easy to read the paper? Sel no -- not at all no -- only marginally so neutral yes -- to some extent yes -- very much 2 Is the paper technically sound (for the time it was written)? Sel no -- not at all no -- only marginally so neutral yes -- to some extent yes -- very much 3 How do you rate the overall presentation? Sel bad not good average pretty good very good 4 Any short suggestions for improvements?
1 Issue 1 2 Issue 2 3 Issue 3 4 Issue 4
Please, print a copy of your form and bring it to the next meeting