UU | IT | DoCS | eh

 

TIC -- Lecture1: CMOS Technology


1. Who are you?

2. Check the TRUE statements for P0
1 The wire delay is proportional to its resistance divided by its capacitance
2 The fraction of chip area reachable in one cycle will be less than 10 percent by year 2011
3 If we continue to build ILP-focused CPUs the performance improvement per year will be around 12 percent
4 The number of memory bits reachable in one cycle will reach its peak by year 2011
5 The access time to L1 caches will decrease with future precess technology (measured in CPU cycles and assuming a constant cache size)
6 The SIA report state that the logic depth between for each pipeline stage will steadily decrease over time
3. Check the TRUE statements for P1
1 One drawback of transmission lines is low bandwidth
2 DNUCA migrates data closer to its usage
3 At high frequencies electrons like to trave close to the surface of a conductor
4 Transmission lines are less sensitive to noise
5 SINGLE-ENDED transmission requires twice as many connections as DIFFERENTIAL transmission for transferring the same amount of data
4. Check the TRUE statements for P2
1 Dynamic power is the dominating power source in current architectures
2 Short-circuit power is projected to become the dominant source of power consumption
3 Leakage power is dependent of temperature
4 Assuming that frequency scaling is trivial and that Intel's recently abandoned motto: FREQUENCY == PERFORMANCE is true: A dynamic power saving techniques that saves 10% of power and slows down the execution by 10% makes sense
5 . Rate paper P0
1 Was it easy to read the paper?
2 Is the paper technically sound (for the time it was written)?
3 How do you rate the overall presentation?
4 Any short suggestions for improvements?

6 . Submit at least two issues to discuss at the meeting
1 Issue 1

2 Issue 2

3 Issue 3

4 Issue 4

7 . Submit two issues to discuss at the meeting
1

2

Please, print a copy of your form and bring it to the next meeting


<eh@it.uu.se>