Erik's Patent Portfolio
[1] WO9912103 
Scalable shared memory multiprocessor system
[2] WO9912102 
A multiprocessing system including cluste optimization mechanisms
[3] WO9734237 
Split transaction snooping bus and method of arbitration
[4] WO9220027 
Method for increasing the speed of data processing in a computer system
[5] WO9000283 
Multiprocessor system including a hierarchical cache memory system
[6] WO8908363 
Telecommunication system for transmitting information between subscribers connected to a bus system
[7] WO0129669 
Communication error reporting mechanism in a multiprocessing computer system
[8] US6332169 
Multiprocessing system configured to perform efficient block copy operations
[9] US6332165 
Multiprocessor computer system employing a mechanism for routing communication traffic through a cluster node having a slice of memory direct
[10] US6308246 
Skewed finite hashing function
[11] US6243742 
Hybrid memory access protocol in a distributed shared memory computer system
[12] US6240501 
Cache-less address translation
[13] US6226671 
Shared memory system for symmetric multiprocessor systems
[14] US6148300 
Hybrid queue and backoff computer resource lock featuring different spin speeds corresponding to multiple-states
[15] US6141692 
Directory-based, shared-memory, scaleable multiprocessor computer system having deadlock-free transaction flow sans flow control protocol
[16] US6078996 
Method for increasing the speed of data processing in a computer system
[17] US5987549 
Method and apparatus providing short latency round-robin arbitration for access to a shared resource
[18] US5983326 
Multiprocessing system including an enhanced blocking mechanism for read-to-share-transactions in a NUMA mode
[19] US5978874 
Implementing snooping on a split-transaction computer system bus
[20] US5960179 
Method and apparatus extending coherence domain beyond a computer system bus
[21] US5958019 
Multiprocessing system configured to perform synchronization operations
[22] US5950226 
Multiprocessing system employing a three-hop communication protocol
[23] US5940860 
Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains
[24] US5926829 
Hybrid NUMA COMA caching system and methods for selecting between the caching modes
[25] US5923847 
Split-SMP computer system configured to operate in a protected mode having repeater which inhibits transaction to local address partiton
[26] US5911052 
Split transaction snooping bus protocol
[27] US5903907 
Skip-level write-through in a multi-level memory of a computer system
[28] US5897657 
Multiprocessing system employing a coherency protocol including a reply count
[29] US5893160 
Deterministic distributed multi-cache coherence method and system
[30] US5893150 
Efficient allocation of cache memory space in a computer system
[31] US5893149 
Flushing of cache memory in a computer system
[32] US5893144 
Hybrid NUMA COMA caching system and methods for selecting between the caching modes
[33] US5892970 
Multiprocessing system configured to perform efficient block copy operations
[34] US5887138 
Multiprocessing computer system employing local an global address spaces and COMA and NUMA access modes
[35] US5881303 
Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue fo each processing subnode
[36] US5878268 
Multiprocessing system configured to store coherenc state within multiple subnodes of a processing node
[37] US5873117 
Method and apparatus for a directory-less memor access protocol in a distributed shared memor computer system
[38] US5864671 
Hybrid memory access protocol for servicing memor access request by ascertaining whether the memor block is currently cached in determinin
[39] US5862357 
Hierarchical SMP computer system
[40] US5862316 
Multiprocessing system having coherency-related erro logging capabilities
[41] US5860159 
Multiprocessing system including an apparatus fo optimizing spin-lock operations
[42] US5860109 
Methods and apparatus for a coherence transformer fo connecting computer system coherence domains
[43] US5852716 
Split-SMP computer system with local domains and top repeater that distinguishes local and globa transactions
[44] US5848254 
Multiprocessing system using an access to a seco memory space to initiate software controlled da prefetch into a first address space
[45] US5842026 
Interrupt transfer management process and system for multi-processor environment
[46] US5835906 
Methods and apparatus for sharing stored data objec in a computer system
[47] US5829034 
Method and apparatus for a coherence transformer wi limited memory for connecting computer syst coherence domains
[48] US5829033 
Optimizing responses in a coherent distribut electronic system including a computer system
[49] US5802566 
Method and system for predicting addresses a prefetching data into a cache memory
[50] US5802563 
Efficient storage of data in computer system wi multiple cache levels
[51] US5796605 
Extended symmetrical multiprocessor address mapping
[52] US5778427 
Method and apparatus for selecting a way of multi-way associative cache by storing waylets in translation structure
[53] US5754877 
Extended symmetrical multiprocessor architecture
[54] US5749095 
Multiprocessing system configured to perfor efficient write operations
[55] US5734922 
Multiprocessing system configured to detect an efficiently provide for migratory data acces patterns
[56] US5710907 
Hybrid NUMA COMA caching system and methods fo selecting between the caching modes
[57] US2001054079 
"Shared memory system for symmetric microprocessor systems"
[58] US2001051977 
Multiprocessing system configured to perform efficient block copy operations
[59] US2001042176 
Skewed finite hashing function
[60] US2001037419 
Multiprocessing system configured to perform efficient block copy operations
[61] US2001027512 
Selective address translation in coherent memory replication
[62] SG74577 
Hybrid numa coma caching system and methods for selecting between the caching modes
[63] SG74576 
Hybrid numa coma caching system and methods for selecting between the coaching modes
[64] SE9101325 
Method and system for predicting addresses and prefetching data into a cache memory
[65] SE8800745 
Multiprocessor system including a hierarchical cache memory system
[66] SE469402 
Method and system for predicting addresses and prefetching data into a cache memory
[67] SE461813 
Multiprocessor architecture comprising processor/memory pairs interconnected with one or more buses in a hierarchical system
[68] SE460750 
No title available.
[69] JP2000076217 
Lock operation optimization system and method for computer system
[70] JP11003322 
Inter-node interruption mechanism in multi-processo system
[71] JP11003280 
Data replacing method in computer system
[72] JP11003279 
Flashing method for cache memory in computer system
[73] JP11003277 
Practically memoryless coherent conversion method an device for connecting computer node with coheren domain
[74] JP10340227 
Multi-processor computer system using local an global address spaces and multi-access mode
[75] JP10214230 
Multiprocessor system adopting coherency protoc including response count
[76] JP10214229 
Method for selecting data to be cached in comput system, computer system and caching device f computer system
[77] JP10214224 
Effective selection for memory storage mode computer system
[78] JP10214222 
Coherence method for connecting computer system wi coherent domain and device therefor
[79] JP10187646 
Split smp computer system
[80] JP10187645 
Multiprocess system constituted for storage in ma subnodes of process node in coherence state
[81] JP10187633 
Method and device for making it possible to sha memory block with external devices
[82] JP10187631 
Extended symmetrical multiprocessor architecture
[83] JP10187630 
Hierarchical smp computer system
[84] JP10187527 
Device and method for preventing access contention
[85] JP10187470 
Multiprocess system provided with device f optimizing spin lock operation
[86] JP10177518 
Hybrid memory access protocol for decentralize common memory computer system
[87] JP10171710 
Multi-process system for executing effective blo copying operation
[88] JP10149342 
Multiprocess system executing prefetch operation
[89] JP10143483 
Multiprocess system constituted so as to detect an efficiently provide migratory data access pattern
[90] JP10143482 
Multiprocessor system for executing efficient writ operation
[91] JP10143477 
Multiprocess system provided with reinforced blockin mechanism for read-to-share transaction in numa mode
[92] JP10143476 
Multiprocess system for executing software fo starting prefetch operation
[93] JP10134014 
Multiprocess system using three-hop communicatio protocol
[94] JP10134009 
Method and device for nondirectory memory acces protocol of decentralized and shared memory compute system
[95] JP10133917 
Multiprocess system with coherency-relative erro logging capability
[96] JP10116253 
Multiprocess system executing synchronous operation
[97] JP10105464 
Cache coherency system for many caches insid multiprocessor
[98] JP10097513 
Node in multiprocessor computer system an multiprocessor computer system
[99] EP1019840 
Scalable shared memory multiprocessor system
[100] EP1010090 
Multiprocessing computer system employing a cluster protection mechanism
[101] EP0965919 
A probabilistic queue lock
[102] EP0832459 
Split transaction snooping bus and method o arbitration
[103] EP0820016 
A multiprocessing system including an enhance blocking mechanism for read-to-share-transactions i a NUMA mode
[104] EP0818733 
A multiprocessing system configured to perform software initiated prefetch operations
[105] EP0818732 
Hybrid memory access protocol in a distributed shared memory computer system
[106] EP0817095 
Extended symmetrical multiprocessor architecture
[107] EP0817093 
A multiprocessor system configured to perform block copy operations
[108] EP0817092 
Extended symmetrical multiprocessor architecture
[109] EP0817081 
Flushing of cache memory in a computer system
[110] EP0817080 
Multi-level cache memory
[111] EP0817079 
Skip-level write-through in a multi-level memory of a computer system
[112] EP0817078 
Allocation of cache memory space in a computer system
[113] EP0817077 
A multiprocessing system configured to perform prefetching operations
[114] EP0817075 
A multiprocessing system configured to perform synchronization operations
[115] EP0817074 
Multiprocessing system employing a three-hop communication protocol
[116] EP0817073 
A multiprocessing system configured to perform efficient write operations
[117] EP0817072 
A multiprocessing system configured to store coherency state within multiple subnodes of a processing node
[118] EP0817071 
A multiprocessing system configured to detect and efficiently provide for migratory data access patterns
[119] EP0817070 
Multiprocessing system employing a coherency protocol including a reply count
[120] EP0817068 
Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains
[121] EP0817064 
Methods and apparatus for a directory less memory access protocol in a distributed shared memory computer system
[122] EP0817062 
Multi-processor computing system and method of controlling traffic flow
[123] EP0817060 
A hierarchical SMP computer system
[124] EP0817051 
A multiprocessing system having coherency related error logging capabilities
[125] EP0817042 
A multiprocessing system including an apparatus for optimizing spin-lock operations
[126] EP0817040 
Methods and apparatus for sharing stored data objects in a computer system
[127] EP0801349 
Deterministic distributed multicache coherence protocol
[128] EP0780770 
Hybrid numa coma caching system and methods for selecting between the caching modes
[129] EP0780769 
Hybrid numa coma caching system and methods for selecting between the caching modes
[130] EP0752662 
Method and apparatus for tagging a multi-way associative cache
[131] EP0582635 
Method for increasing the speed of data processing in a computer system.
[132] EP0424432 
Multiprocessor system including a hierarchical cache memory system
[133] DE69228380T 
Method and system for predicting addresses and prefetching data into a cache memory
[134] DE69228380D 
Method and system for predicting addresses and prefetching data into a cache memory
[135] DE68928454T 
Multiprocessor system including a hierarchical cache memory system
[136] DE68928454D 
Multiprocessor system including a hierarchical cache memory system
[137] AU8017100 
Communication error reporting mechanism in a multiprocessing computer system
[138] AT176534T 
Method and system for predicting addresses and prefetching data into a cache memory
[139] AT160454T 
Multiprocessor system including a hierarchical cache memory system